公开(公告)号：US07651909B2

公开(公告)日：2010-01-26

申请号：US11377160

申请日：2006-03-15

Applicant: Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

IPC: H01L21/8242

CPC classification number: H01L28/40

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract translation: 描述了用于制造金属 - 绝缘体 - 金属电容器的方法。 在基板上形成第一金属层。 在第一金属层的表面进行等离子体处理。 然后，依次在第一金属层上形成第一氧化物层，氮化物层和第二氧化物层。 此后，在第二氧化物层上形成第二金属层。 第二金属层，第二氧化物层，氮化物层，第一氧化物层和第一金属层被定义为形成金属 - 绝缘体 - 金属电容器。

公开(公告)号：US20080090020A1

公开(公告)日：2008-04-17

申请号：US11951244

申请日：2007-12-05

Applicant: Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

IPC: B05D3/04 ,  C23C14/35

CPC classification number: H01L28/40

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract translation: 描述了用于制造金属 - 绝缘体 - 金属电容器的方法。 在基板上形成第一金属层。 在第一金属层的表面进行等离子体处理。 然后，依次在第一金属层上形成第一氧化物层，氮化物层和第二氧化物层。 此后，在第二氧化物层上形成第二金属层。 第二金属层，第二氧化物层，氮化物层，第一氧化物层和第一金属层被定义为形成金属 - 绝缘体 - 金属电容器。

公开(公告)号：US20070218626A1

公开(公告)日：2007-09-20

申请号：US11377160

申请日：2006-03-15

Applicant: Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

IPC: H01L21/8242

CPC classification number: H01L28/40

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract translation: 描述了用于制造金属 - 绝缘体 - 金属电容器的方法。 在基板上形成第一金属层。 在第一金属层的表面进行等离子体处理。 然后，依次在第一金属层上形成第一氧化物层，氮化物层和第二氧化物层。 此后，在第二氧化物层上形成第二金属层。 第二金属层，第二氧化物层，氮化物层，第一氧化物层和第一金属层被定义为形成金属 - 绝缘体 - 金属电容器。

公开(公告)号：US06864150B2

公开(公告)日：2005-03-08

申请号：US10384287

申请日：2003-03-06

Applicant: Ping-Wei Lin ,  Gwo-Chyuan Kuoh ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Gwo-Chyuan Kuoh ,  Chao-Sheng Chiang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76232

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract translation: 本发明公开了浅沟槽隔离（STI）的制造方法。 通过利用沉积具有特定厚度和不同消光系数（k）的两层SiON作为ARC，包括：（a）在衬底上沉积衬垫氧化物/氮化硅作为用于蚀刻的硬掩模; （b）在所述氮化硅上沉积一层高消光系数SiON，然后沉积一层低消光系数SiON作为ARC; （c）通过使用STI掩模曝光并显影以形成所述STI的蚀刻掩模; （d）蚀刻所述SiON，氮化硅，衬垫氧化物和所述衬底以形成浅沟槽; （e）在浅沟槽的侧壁和底部生长氧化层，以消除损坏并减少泄漏; （f）在所述浅沟槽和所述氮化硅上沉积氧化物层以填充所述浅沟槽; （g）通过CMP平面化。

公开(公告)号：US20050186796A1

公开(公告)日：2005-08-25

申请号：US10784186

申请日：2004-02-24

Applicant: Ping-Wei Lin ,  Chao-Sheng Chiang ,  Kuo-Chuan Kuo

Inventor： Ping-Wei Lin ,  Chao-Sheng Chiang ,  Kuo-Chuan Kuo

IPC: H01L21/311 ,  H01L21/316 ,  H01L21/469 ,  H01L21/473 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76837

Abstract: A method for gap filling between metal-metal lines is provided so that a first dielectric layer forms on a surface and side wall of a plurality of metal lines thereon which is called partially HDP deposition. Then, a portion of the first dielectric layer is removed by a high-density plasma with Ar/O2 to sputter so that a portion of side wall of metal lines is exposed. Afterwards, a second dielectric layer is formed on the first dielectric layer by a method of high density plasma oxide deposition so that the metal lines are completely covered.

Abstract translation: 提供金属 - 金属线之间的间隙填充的方法，使得第一介电层在其上的多个金属线的表面和侧壁上形成，称为部分HDP沉积。 然后，通过具有Ar / O 2 N的高密度等离子体去除第一介电层的一部分，以溅射金属线的侧壁的一部分。 之后，通过高密度等离子体氧化物沉积的方法在第一介电层上形成第二电介质层，使得金属线被完全覆盖。

公开(公告)号：US6071794A

公开(公告)日：2000-06-06

申请号：US323746

申请日：1999-06-01

Applicant: Ping-Wei Lin ,  Ming-Kuan Kao ,  Jui-Ping Li

Inventor： Ping-Wei Lin ,  Ming-Kuan Kao ,  Jui-Ping Li

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L21/76

CPC classification number: H01L21/28194 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/78 ,  H01L21/28211 ,  H01L29/4236

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

公开(公告)号：US20060219924A1

公开(公告)日：2006-10-05

申请号：US11137456

申请日：2005-05-26

Applicant: Tzong-Sheng Lee ,  Ping-Wei Lin ,  Hsiang-Fu Chen ,  Hung-Ti Li ,  Jeng-Long Ou

Inventor： Tzong-Sheng Lee ,  Ping-Wei Lin ,  Hsiang-Fu Chen ,  Hung-Ti Li ,  Jeng-Long Ou

IPC: G01J5/02

CPC classification number: G01J5/04 ,  G01J1/02 ,  G01J1/0252 ,  G01J5/045 ,  G01J5/061 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: An infrared imaging sensor and a vacuum packaging method thereof are described. The infrared imaging sensor includes a ceramic base, a metal cap and an infrared filter. The ceramic base has an infrared imaging chip attached thereon and the metal cap includes a getter deposited on an inner surface of the metal cap. The infrared filter seals an opening of the metal cap. The ceramic base, the metal cap and the infrared filter are heated in a vacuum chamber to activate the getter, and to solder the ceramic base, the metal cap and the infrared filter together thereby vacuum packaging the infrared imaging sensor.

Abstract translation: 描述了红外成像传感器及其真空包装方法。 红外成像传感器包括陶瓷基座，金属帽和红外线过滤器。 陶瓷基座上安装有红外成像芯片，金属盖包括沉积在金属盖的内表面上的吸气剂。 红外线过滤器密封金属盖的开口。 陶瓷基座，金属帽和红外线过滤器在真空室中加热以激活吸气剂，并且将陶瓷基底，金属帽和红外线过滤器焊接在一起，从而真空包装红外成像传感器。

公开(公告)号：US06551900B1

公开(公告)日：2003-04-22

申请号：US09547730

申请日：2000-04-12

Applicant: Yifu Chung ,  Leon Chang ,  Ping-Wei Lin

Inventor： Yifu Chung ,  Leon Chang ,  Ping-Wei Lin

IPC: H01L2176

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/66734 ,  H01L29/7813

Abstract: A method for improving gate oxide thinning issue at trench corners is disclosed. The method comprises steps as follows. Firstly, a silicon substrate having a trench therein is provided. HDPCVD technology to form a first oxide layer on the sidewall and the bottom of the trench is carried out. After performing an etchback to leave the first oxide layer on the bottom of the trench, a second oxide layer is formed on the first oxide layer and on sidewalls of the trench by LPCVD technology. Thereafter, an isotropic etching is performed so as to remove a substantially portion of the second oxide layer and leave a remnant portion of second oxide layer on the trench corners. As a consequently, the trench corners are smooth. Finally, a thermal oxidation to form a third oxide layer on the sidewall of the trench is carried achieved to accomplish the gate oxide formation.

Abstract translation: 公开了一种在沟槽角改善栅极氧化物薄化问题的方法。 该方法包括以下步骤。 首先，提供其中具有沟槽的硅衬底。 HDPCVD技术在沟槽的侧壁和底部上形成第一氧化物层。 在进行回蚀以在沟槽的底部离开第一氧化物层之后，通过LPCVD技术在第一氧化物层和沟槽的侧壁上形成第二氧化物层。 此后，进行各向同性蚀刻以去除第二氧化物层的大致部分，并且在沟槽角上留下第二氧化物层的残余部分。 因此，沟渠的角落是光滑的。 最后，实现在沟槽的侧壁上形成第三氧化物层的热氧化以实现栅极氧化物的形成。

公开(公告)号：US06355974B1

公开(公告)日：2002-03-12

申请号：US09588110

申请日：2000-05-31

Applicant: Ping-Wei Lin ,  Ming-Kuan Kao ,  Jui-Ping Li

Inventor： Ping-Wei Lin ,  Ming-Kuan Kao ,  Jui-Ping Li

IPC: H01L2904

CPC classification number: H01L21/28194 ,  H01L21/28211 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/78

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract translation: 公开了一种防止在侧壁和底部绝缘体之间的接合处形成绝缘层的较薄部分，特别是栅极氧化物层的方法。 首先，在沟槽的侧壁和底部形成衬垫氧化物层。 接下来，在沟槽的下部形成底部氧化物。 然后，通过湿蚀刻去除底部氧化物的上部和暴露的焊盘氧化物层，以留下具有凹面的底部氧化物。 接下来，在沟槽的暴露的侧壁上生长保形栅极氧化物层。

公开(公告)号：US06261930B1

公开(公告)日：2001-07-17

申请号：US09287440

申请日：1999-04-07

Applicant: Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao ,  Yi-Shin Chang

Inventor： Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao ,  Yi-Shin Chang

IPC: H01L2120

CPC classification number: H01L28/84

Abstract: An irradiation process method for forming polysilicon layer is disclosed. The method includes firstly forming an alpha-silicon layer on substrate. Then the temperature of the UHV-CVD chamber is increased and the wafer is sent into the chamber. Gas is then intermittently conducted into the vacuum-chamber apparatus. While increasing the temperature of the vacuum-chamber apparatus, the whole throughput thus increases and the process-time for the polysilicon layer thus decreases. Finally, the electrical capacity thus increases by forming the polysilicon layer.

Abstract translation: 公开了一种用于形成多晶硅层的照射处理方法。 该方法包括首先在基底上形成α-硅层。 然后，UHV-CVD室的温度升高，将晶片送入室内。 然后将气体间歇地传导到真空室装置中。 在增加真空室装置的温度的同时，整体生产量因此增加，因此多晶硅层的处理时间减少。 最后，通过形成多晶硅层而增加电容量。