公开(公告)号：US09536883B2

公开(公告)日：2017-01-03

申请号：US13548123

申请日：2012-07-12

申请人： Frank Hui ,  Neal Kistler

发明人： Frank Hui ,  Neal Kistler

IPC分类号： H01L29/00 ,  H01L27/10 ,  H01L23/525

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.

摘要翻译： 根据一个示例性实施方式，双反熔丝结构包括与第一可编程门相邻的公共半导体鳍片中的第一通道。 双反熔丝结构还包括与第二可编程门相邻的所述公共半导体鳍片中的第二通道。 在第一通道和第一可编程门之间形成第一反熔丝。 此外，在第二通道和第二可编程门之间形成第二反熔丝。 第一可编程门可以在公共半导体鳍片的第一侧壁上，并且可以包括第一栅极电介质和第一电极。 第二可编程门可以在公共半导体鳍片的第二侧壁上，并且可以包括第二栅极电介质和第二电极。

公开(公告)号：US20140015095A1

公开(公告)日：2014-01-16

申请号：US13548123

申请日：2012-07-12

申请人： Frank Hui ,  Neal Kistler

发明人： Frank Hui ,  Neal Kistler

IPC分类号： H01L23/525

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.

摘要翻译： 根据一个示例性实施方式，双反熔丝结构包括与第一可编程门相邻的公共半导体鳍片中的第一通道。 双反熔丝结构还包括与第二可编程门相邻的所述公共半导体鳍片中的第二通道。 在第一通道和第一可编程门之间形成第一反熔丝。 此外，在第二通道和第二可编程门之间形成第二反熔丝。 第一可编程门可以在公共半导体鳍片的第一侧壁上，并且可以包括第一栅极电介质和第一电极。 第二可编程门可以在公共半导体鳍片的第二侧壁上，并且可以包括第二栅极电介质和第二电极。

公开(公告)号：US09048201B2

公开(公告)日：2015-06-02

申请号：US13167152

申请日：2011-06-23

申请人： Frank Hui ,  Neal Kistler ,  Don Bautista

发明人： Frank Hui ,  Neal Kistler ,  Don Bautista

IPC分类号： H01L23/544 ,  H01L23/58 ,  H01L29/00 ,  H01L21/44 ,  H01L21/66

CPC分类号： H01L22/32 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips.

摘要翻译： 本发明涉及半导体晶片，集成电路产品及其制造方法，其具有由划线分开的多个非分割芯片，包括多个密封环，每个密封环围绕相应的芯片并且设置在相应的芯片之间 和相邻划线。 良好的电阻器设置在设置在划线中的密封环和探针垫的下方。 特别地，至少一个探针焊盘通过至少一个阱电阻器耦合到至少一个芯片。

公开(公告)号：US08816421B2

公开(公告)日：2014-08-26

申请号：US13460336

申请日：2012-04-30

申请人： Frank Hui ,  Neal Kistler

发明人： Frank Hui ,  Neal Kistler

IPC分类号： H01L29/788

CPC分类号： G11C13/048 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881

摘要： According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.

摘要翻译： 根据一个示例性实施方式，半导体器件包括位于第一半导体鳍片中的沟道，源极和漏极。 通道位于源极和漏极之间。 半导体器件还包括位于第二半导体鳍片中的控制栅极。 浮置栅极位于第一半导体鳍片和第二半导体鳍片之间。 半导体器件还可以包括位于浮置栅极和第一半导体鳍片之间的第一介电区域和位于浮置栅极和第二半导体鳍片之间的第二介电区域。

公开(公告)号：US20130285135A1

公开(公告)日：2013-10-31

申请号：US13460336

申请日：2012-04-30

申请人： Frank Hui ,  Neal Kistler

发明人： Frank Hui ,  Neal Kistler

IPC分类号： H01L29/788

CPC分类号： G11C13/048 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881

摘要： According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.

摘要翻译： 根据一个示例性实施方式，半导体器件包括位于第一半导体鳍片中的沟道，源极和漏极。 通道位于源极和漏极之间。 半导体器件还包括位于第二半导体鳍片中的控制栅极。 浮置栅极位于第一半导体鳍片和第二半导体鳍片之间。 半导体器件还可以包括位于浮置栅极和第一半导体鳍片之间的第一介电区域和位于浮置栅极和第二半导体鳍片之间的第二介电区域。

公开(公告)号：US20120326146A1

公开(公告)日：2012-12-27

申请号：US13167152

申请日：2011-06-23

申请人： Frank Hui ,  Neal Kistler ,  Don Bautista

发明人： Frank Hui ,  Neal Kistler ,  Don Bautista

IPC分类号： H01L23/58 ,  H01L21/02 ,  H01L29/86

CPC分类号： H01L22/32 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips.

摘要翻译： 本发明涉及半导体晶片，集成电路产品及其制造方法，其具有由划线分开的多个非分割芯片，包括多个密封环，每个密封环围绕相应的芯片并且设置在相应的芯片之间 和相邻划线。 良好的电阻器设置在设置在划线中的密封环和探针垫的下方。 特别地，至少一个探针焊盘通过至少一个阱电阻器耦合到至少一个芯片。