公开(公告)号：US08589636B2

公开(公告)日：2013-11-19

申请号：US12801869

申请日：2010-06-29

Applicant: Akihiro Waku ,  Naoya Ishimura ,  Hiroyuki Kojima

Inventor： Akihiro Waku ,  Naoya Ishimura ,  Hiroyuki Kojima

IPC: G06F12/00

CPC classification number: G06F12/0888

Abstract: A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.

Abstract translation: 高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径 当从算术处理单元向主存储单元写入数据时，连接单元。

公开(公告)号：US08327079B2

公开(公告)日：2012-12-04

申请号：US12636523

申请日：2009-12-11

Applicant: Koken Shimizuno ,  Naoya Ishimura

Inventor： Koken Shimizuno ,  Naoya Ishimura

IPC: G06F12/00

CPC classification number: G06F12/0888 ,  G06F9/3824 ,  G06F9/3885 ,  G06F12/0855 ,  G06F12/0857

Abstract: A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.

Abstract translation: 高速缓冲存储器控制装置包括：确定单元，用于确定从例如每个核心提供的命令是否在执行命令期间访问高速缓冲存储器; 以及路径切换单元，用于将被确定为访问高速缓冲存储器的命令置于流水线处理中，并且将未被确定为不访问高速缓冲存储器的命令直接输出到外部单元，而不将命令输入流水线处理。

公开(公告)号：US20100332758A1

公开(公告)日：2010-12-30

申请号：US12801869

申请日：2010-06-29

Applicant: Akihiro Waku ,  Naoya Ishimura ,  Hiroyuki Kojima

Inventor： Akihiro Waku ,  Naoya Ishimura ,  Hiroyuki Kojima

IPC: G06F12/08 ,  G06F12/00 ,  G06F9/302

CPC classification number: G06F12/0888

Abstract: A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.

Abstract translation: 高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径 当从算术处理单元向主存储单元写入数据时，连接单元。

公开(公告)号：US07849230B2

公开(公告)日：2010-12-07

申请号：US12222228

申请日：2008-08-05

Applicant: Naoya Ishimura ,  Hiroyuki Kojima

Inventor： Naoya Ishimura ,  Hiroyuki Kojima

IPC: G06F3/00 ,  G06F13/00 ,  G06F7/38

CPC classification number: G06F13/14

Abstract: A request control apparatus and a request control method are configured such that when an A type request that is an overtaking acceptable request allowed to overtake and to be overtaken among the other requests is turned to a retry matter on a pipeline, a request-order control unit performs an information renewal such that the A type request is rearranged to a place immediately preceding a B type request that is an overtaking inhibited request inhibited to overtake or to be overtaken among the other requests, and a request fetching unit fetches requests from ports by using the information renewed by the request-order control unit. Moreover, the request-order control unit is configured to perform request order control per request source.

Abstract translation: 请求控制装置和请求控制方法被配置为使得当超过可接受请求的A类型请求被允许超过并且在其他请求中被超时时，将被转到管线上的重试事务，请求命令控制 单元执行信息更新，使得A类型请求被重新排列到超过禁止请求的B类型请求之前禁止超过或超过其他请求的请求，并且请求提取单元从端口获取请求 使用由请求单控制单元更新的信息。 此外，请求顺序控制部被配置为对每个请求源执行请求顺序控制。

公开(公告)号：US20090064153A1

公开(公告)日：2009-03-05

申请号：US12199447

申请日：2008-08-27

Applicant: Naoya ISHIMURA ,  Hideyuki Unno

Inventor： Naoya ISHIMURA ,  Hideyuki Unno

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/315

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/5011 ,  G06F2209/5021 ,  G06F2209/507

Abstract: When selecting one command within a processor from a plurality of command queues vested with order of priority, the order of priority assigned to the plurality of command queues is dynamically changed so as to select a command, on a priority basis, from a command queue vested with a higher priority from among the plurality of command queues in accordance with the post-change order of priority.

Abstract translation: 当从多个以优先级顺序赋予的命令队列中选择一个命令时，分配给多个命令队列的优先级顺序被动态地改变，从而优先地从命令队列中选择一个命令 根据优先级的改变后顺序，从多个命令队列中具有较高的优先级。

公开(公告)号：US20120260056A1

公开(公告)日：2012-10-11

申请号：US13528153

申请日：2012-06-20

Applicant: Toru Hikichi ,  Naoya Ishimura

Inventor： Toru Hikichi ,  Naoya Ishimura

IPC: G06F12/02

CPC classification number: G06F12/0862 ,  G06F9/30043 ,  G06F9/30047 ,  G06F2212/6028

Abstract: A processor includes: a first storage that stores data stored in a main storage; a processor that outputs an instruction for loading data from the main storage into the first storage; a second storage that holds a instruction until the first storage receives the data requested by the instruction; a first controller that reads the data requested by an instruction from the first storage and transfers the requested data to the processor, when the requested data is in the first storage, or but, transfers the received instruction to the main storage, when the requested data is not in the first storage and an instruction requesting the same data as the requested data is not in the second storage; and a second controller that completes reading the data requested by an instruction, when an instruction requesting the same data as the requested data is in the second storage.

Abstract translation: 处理器包括：存储存储在主存储器中的数据的第一存储器; 输出用于将数据从主存储器加载到第一存储器中的指令的处理器; 第二存储器，其保持指令，直到所述第一存储器接收到由所述指令请求的数据; 第一控制器，当所请求的数据在第一存储器中时，读取来自第一存储器的指令所请求的数据并将所请求的数据传送到处理器，或者当所请求的数据被传送到主存储器时 不在第一存储器中，并且请求与所请求的数据相同的数据的指令不在第二存储器中; 以及当请求与所请求的数据相同的数据的指令在第二存储器中时，完成读取由指令请求的数据的第二控制器。

公开(公告)号：US20090013105A1

公开(公告)日：2009-01-08

申请号：US12222228

申请日：2008-08-05

Applicant: Naoya Ishimura ,  Hiroyuki Kojima

Inventor： Naoya Ishimura ,  Hiroyuki Kojima

IPC: G06F3/00

CPC classification number: G06F13/14

Abstract: A request control apparatus and a request control method are configured such that when an A type request that is an overtaking acceptable request allowed to overtake and to be overtaken among the other requests is turned to a retry matter on a pipeline, a request-order control unit performs an information renewal such that the A type request is rearranged to a place immediately preceding a B type request that is an overtaking inhibited request inhibited to overtake or to be overtaken among the other requests, and a request fetching unit fetches requests from ports by using the information renewed by the request-order control unit. Moreover, the request-order control unit is configured to perform request order control per request source.

Abstract translation: 请求控制装置和请求控制方法被配置为使得当超过可接受请求的A类型请求被允许超过并且在其他请求之中被超时时，被转换为管道上的重试，请求命令控制 单元执行信息更新，使得A类型请求被重新排列到超过禁止请求的B类型请求之前禁止超过或超过其他请求的请求，并且请求提取单元从端口获取请求 使用由请求单控制单元更新的信息。 此外，请求顺序控制部被配置为对每个请求源执行请求顺序控制。

公开(公告)号：US20080293326A1

公开(公告)日：2008-11-27

申请号：US12120596

申请日：2008-05-14

Applicant: Naoya Ishimura

Inventor： Naoya Ishimura

IPC: A63H3/02 ,  A63H3/44

CPC classification number: A63H3/44 ,  D01F6/60 ,  D01F8/12

Abstract: Hair for toys which is constituted of filaments made of an alcohol-soluble resin is disclosed. The hair for toys may also be hair for toys which is constituted of filaments made of a composite resin made up of a core and a sheath, where at least one of the resin of the core and that of the sheath is an alcohol-soluble resin.

Abstract translation: 公开了由醇溶性树脂制造的由长丝构成的玩具用毛发。 用于玩具的头发也可以是由由芯和护套组成的复合树脂制成的长丝构成的玩具头，其中至少一个核心和护套的树脂是醇溶性树脂 。

公开(公告)号：US6159598A

公开(公告)日：2000-12-12

申请号：US447240

申请日：1999-11-23

Applicant: Naoya Ishimura

Inventor： Naoya Ishimura

IPC: C08J5/00 ,  A41G3/00 ,  A63H3/44 ,  D01F1/10 ,  D01F8/04 ,  D01F8/06 ,  D01F8/10 ,  D01F8/12 ,  D01F8/14 ,  D01F8/16 ,  D01F8/00

CPC classification number: A41G3/0083 ,  A63H3/44 ,  D01F1/10 ,  D01F8/04 ,  D01F8/06 ,  D01F8/10 ,  D01F8/12 ,  D01F8/14 ,  D01F8/16 ,  Y10T428/2924

Abstract: In a core/sheath type temperature-sensitive shape-transformable composite filament comprising a thermoplastic resin (A) and a thermoplastic polymer (B) having a glass transition temperature within the range of from 0.degree. C. to 70.degree. C., the composite filament is constituted in proportions satisfying the following expressions (1), (2) and (3).In the core;(A)/(B)=5/95 to 90/10 (% by weight) (1)In the sheath;(A)/(B)=100/0 to 50/50 (% by weight) (2)Core/sheath=10/90 to 95/5 (% by weight) (3)The filament is useful as doll hair the hair style of which is thermally shape-transformable to any desired shapes even by infants, and is easily fixable to the transformed shape by cooling.

Abstract translation: 在包含热塑性树脂（A）和玻璃化转变温度在0℃至70℃范围内的热塑性聚合物（B）的芯/鞘型温度敏感型可变形复合长丝中，复合材料 灯丝以满足以下表达式（1），（2）和（3）的比例构成。 核心部分;（A）/（B）= 5/95〜90/10（重量％）（1）鞘内（A）/（B）= 100/0〜50/50 ）（2）芯/皮= 10/90〜95/5（重量％）（3）长丝可用作娃娃头发，发型也可以由婴儿发热成形成任意形状， 通过冷却可以很容易地固定到变形的形状上。

公开(公告)号：US08713216B2

公开(公告)日：2014-04-29

申请号：US12805193

申请日：2010-07-16

Applicant: Kumiko Endo ,  Naoya Ishimura

Inventor： Kumiko Endo ,  Naoya Ishimura

IPC: G06F13/00

CPC classification number: G06F13/1673 ,  G06F13/1684

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.

Abstract translation: 处理器 响应于来自处理部分的请求，第一和第二存储器控制器分别经由第一和第二总线将第一和第二数据项传送到处理部分。 当通过第一和第二总线同时执行数据项的传送时，其中一个数据项由缓冲器控制器传送到处理部分，另一个数据项由缓冲器控制器存储在缓冲器中。 然后，在数据项中的一个数据项的传送终止之后，其他数据项由缓冲器控制器从缓冲器传送到处理部分。