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    METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE
    1.
    发明申请
    METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE 有权
    编写非易失性存储器件的方法

    公开(公告)号：US20130028018A1

    公开(公告)日：2013-01-31

    申请号：US13546120

    申请日：2012-07-11

    申请人： Yong-Sung Cho ,  Nam-Hee Lee ,  Sang-Yong Yoon

    发明人： Yong-Sung Cho ,  Nam-Hee Lee ,  Sang-Yong Yoon

    IPC分类号： G11C16/04

    CPC分类号： G11C16/34 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3431 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459

    摘要： In method of programming a nonvolatile memory device, multi-bit data are loaded into a plurality of page buffers. Multi-level cells included in a multi-level cell block are programmed to a plurality of intermediate program states including a first intermediate program state and a second intermediate program state which is higher than the first intermediate program state based on the multi-bit data. Whether the multi-level cells are programmed to the plurality of intermediate program states is verified. Cell group information for the first intermediate program state is generated by checking whether a result of the verification for the second intermediate program state satisfies a predetermined criterion. The multi-level cells are programmed to a plurality of target program states corresponding to the multi-bit data based on the cell group information.

    摘要翻译： 在非易失性存储器件的编程方法中，将多位数据加载到多个页缓冲器中。 包括在多电平单元块中的多电平单元被编程为多个中间程序状态，包括基于多位数据高于第一中间程序状态的第一中间程序状态和第二中间程序状态。 验证多级单元是否被编程到多个中间程序状态。 通过检查第二中间程序状态的验证结果是否满足预定标准来生成用于第一中间程序状态的单元组信息。 基于小区组信息，多级小区被编程为与多比特数据相对应的多个目标程序状态。

    FLASH MEMORY DEVICE AND READING METHOD THEREOF
    2.
    发明申请
    FLASH MEMORY DEVICE AND READING METHOD THEREOF 有权
    闪存存储器件及其读取方法

    公开(公告)号：US20110305087A1

    公开(公告)日：2011-12-15

    申请号：US13155462

    申请日：2011-06-08

    申请人： Jong-hoon Lee ,  Nam-hee Lee

    发明人： Jong-hoon Lee ,  Nam-hee Lee

    IPC分类号： G11C16/04 ,  G11C16/26

    CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/26

    摘要： A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through bit lines and having page buffers. The page buffers include a bit line connection unit connected between a corresponding bit line and a sensing node, that controls a voltage of the sensing node according to the sensing node voltage control signal; a precharge unit which precharges the sensing node according to the precharge voltage responsive to a precharge control signal; and a data input/output unit sensing a voltage level of the sensing node responsive to a latch control signal and outputting the data of the selected memory cell.

    摘要翻译： 一种闪存装置，其中通过控制感测节点的电压和对应的读取方法来增加关闭单元余量，其中闪存装置包括存储单元阵列; 感测节点电压控制器，产生预充电电压和感测节点电压控制信号; 以及通过位线连接到存储单元阵列并具有页缓冲器的页缓冲器单元。 页缓冲器包括连接在相应位线和感测节点之间的位线连接单元，其根据感测节点电压控制信号来控制感测节点的电压; 预充电单元，其响应于预充电控制信号，根据预充电电压对感测节点进行预充电; 以及数据输入/输出单元，其响应于锁存控制信号感测感测节点的电压电平，并输出所选择的存储器单元的数据。

    Flip cover plate for mobile terminal
    3.
    发明授权
    Flip cover plate for mobile terminal 有权
    手机终端翻盖板

    公开(公告)号：US09391663B2

    公开(公告)日：2016-07-12

    申请号：US14433034

    申请日：2013-12-11

    申请人： Nam Woon Yun ,  Min Seok Yun ,  Nam Hee Lee

    发明人： Nam Woon Yun ,  Min Seok Yun ,  Nam Hee Lee

    IPC分类号： H04M1/00 ,  H04B1/3888 ,  H04M1/02

    CPC分类号： H04B1/3888 ,  A45C11/00 ,  A45C2011/002 ,  A45C2200/05 ,  H04M1/0202 ,  H04M1/0214 ,  H04M1/185

    摘要： The present invention relates to a flip cover plate (10) for a mobile terminal, the plate comprising: a cover plate inserted into a flip cover which opens and closes the front portion of the mobile terminal; and a transparent window coupled to one side of the cover plate and exposing a portion of a liquid crystal of the mobile terminal to the outside when the flip cover is positioned at the front portion of the mobile terminal, wherein the transparent window is configured to be bonded to at least one surface of the cover plate corresponding to in opening of the flip cover. Accordingly, the present invention has an advantage of maximizing productivity compared to production through one by one cutting processes by means of a conventional numerically controlled machine tool. Furthermore, since the transparent window is not simultaneously molded when the cover plate is injection-molded, the present invention has advantages of simplifying the shape of a mold, thereby being capable of reducing manufacturing costs, as well as reducing manufacturing time and also the failure rate of products since the manufacturing of parts proceeds in parallel.

    摘要翻译： 本发明涉及一种用于移动终端的翻盖板（10），该板包括：插入翻盖的盖板，该盖板打开和关闭移动终端的前部; 以及透明窗口，其联接到所述盖板的一侧，并且当所述翻盖位于所述移动终端的前部时将所述移动终端的液晶的一部分暴露于外部，其中所述透明窗口被配置为 粘合到盖板的至少一个表面上，对应于翻盖的打开。 因此，本发明具有通过常规的数控机床通过一个接一个的切割工艺最大化生产率的优点。 此外，由于在盖板注塑时透明窗不同时成型，本发明具有简化模具形状的优点，从而能够降低制造成本，并且减少制造时间和故障 零件生产后的产品率同时进行。

    Flash memory device and reading method thereof
    4.
    发明授权
    Flash memory device and reading method thereof 有权
    闪存装置及其读取方法

    公开(公告)号：US08593867B2

    公开(公告)日：2013-11-26

    申请号：US13155462

    申请日：2011-06-08

    申请人： Jong-hoon Lee ,  Nam-hee Lee

    发明人： Jong-hoon Lee ,  Nam-hee Lee

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/00

    CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/26

    摘要： A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through bit lines and having page buffers. The page buffers include a bit line connection unit connected between a corresponding bit line and a sensing node, that controls a voltage of the sensing node according to the sensing node voltage control signal; a precharge unit which precharges the sensing node according to the precharge voltage responsive to a precharge control signal; and a data input/output unit sensing a voltage level of the sensing node responsive to a latch control signal and outputting the data of the selected memory cell.

    摘要翻译： 一种闪存装置，其中通过控制感测节点的电压和对应的读取方法来增加关闭单元余量，其中闪存装置包括存储单元阵列; 感测节点电压控制器，产生预充电电压和感测节点电压控制信号; 以及通过位线连接到存储单元阵列并具有页缓冲器的页缓冲器单元。 页缓冲器包括连接在相应位线和感测节点之间的位线连接单元，其根据感测节点电压控制信号来控制感测节点的电压; 预充电单元，其响应于预充电控制信号，根据预充电电压对感测节点进行预充电; 以及数据输入/输出单元，其响应于锁存控制信号感测感测节点的电压电平，并输出所选择的存储器单元的数据。

    Method of programming a nonvolatile memory device
    5.
    发明授权
    Method of programming a nonvolatile memory device 有权
    非易失性存储器件编程方法

    公开(公告)号：US08767475B2

    公开(公告)日：2014-07-01

    申请号：US13546120

    申请日：2012-07-11

    申请人： Yong-Sung Cho ,  Nam-hee Lee ,  Sang-Yong Yoon

    发明人： Yong-Sung Cho ,  Nam-hee Lee ,  Sang-Yong Yoon

    IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

    CPC分类号： G11C16/34 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3431 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459

    摘要： In method of programming a nonvolatile memory device, multi-bit data are loaded into a plurality of page buffers. Multi-level cells included in a multi-level cell block are programmed to a plurality of intermediate program states including a first intermediate program state and a second intermediate program state which is higher than the first intermediate program state based on the multi-bit data. Whether the multi-level cells are programmed to the plurality of intermediate program states is verified. Cell group information for the first intermediate program state is generated by checking whether a result of the verification for the second intermediate program state satisfies a predetermined criterion. The multi-level cells are programmed to a plurality of target program states corresponding to the multi-bit data based on the cell group information.

    摘要翻译： 在非易失性存储器件的编程方法中，将多位数据加载到多个页缓冲器中。 包括在多电平单元块中的多电平单元被编程为多个中间程序状态，包括基于多位数据高于第一中间程序状态的第一中间程序状态和第二中间程序状态。 验证多级单元是否被编程到多个中间程序状态。 通过检查第二中间程序状态的验证结果是否满足预定标准来生成用于第一中间程序状态的单元组信息。 基于小区组信息，多级小区被编程为与多比特数据相对应的多个目标程序状态。