公开(公告)号：US20080155217A1

公开(公告)日：2008-06-26

申请号：US11644161

申请日：2006-12-22

申请人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

发明人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F2212/2022

摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.

摘要翻译： 半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

公开(公告)号：US5867438A

公开(公告)日：1999-02-02

申请号：US726168

申请日：1996-10-04

申请人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括读取或写入存储单元的数据的数据读/写电路，刷新存储在存储单元中的数据的自刷新电路，以及供给单元 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US07934051B2

公开(公告)日：2011-04-26

申请号：US12012390

申请日：2008-02-01

申请人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

发明人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

IPC分类号： G06F12/00

CPC分类号： G11C16/22

摘要： The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region.

摘要翻译： 本发明提供半导体器件和控制半导体器件的方法，该半导体器件包括包括非易失性存储器单元的存储区域; 程序禁止信息单元，程序禁止信息单元存储要用于确定是否禁止或允许在对应于程序禁止信息单元的多个存储器区域中进行编程的程序禁止信息; 第一禁止信息控制电路，禁止将程序禁止信息从程序禁止状态改变为允许相对于存储区域的状态的程序，所述存储区域是所述多个对应的存储区域中的一个，基于第一禁止信息 用于确定是否禁止将程序禁止信息从程序禁止状态改变为相对于对应的存储区域的程序允许状态; 以及第二禁止信息控制电路，其基于第二禁止信息来禁止程序禁止信息从允许状态到相对于存储区域的程序禁止状态的程序的改变，所述第二禁止信息控制电路用于确定是否禁止改变 程序禁止信息从允许状态到相对于对应的存储器区域的程序禁止状态的程序。

公开(公告)号：US07895406B2

公开(公告)日：2011-02-22

申请号：US11986332

申请日：2007-11-20

申请人： Mitsuhiro Nagao

发明人： Mitsuhiro Nagao

IPC分类号： G06F12/00

CPC分类号： G11C7/24 ,  G11C8/20 ,  G11C16/22

摘要： To provide a memory device and a password storing method thereof, according to which an improved security function is realized by resourcefully designing the storage position and/or storing order of password data stored in the memory device to prevent unauthorized password acquisition. The memory device makes a determination of whether or not rewriting and/or reading of data is permitted by verification of a password, the memory device comprising a plurality of partial memory areas which store a plurality of partial bit strings that comprise a bit string of the password, and wherein the plurality of partial memory areas are located apart from each other in a memory cell array.

摘要翻译： 为了提供一种存储装置和密码存储方法，根据该存储装置和密码存储方法，通过对存储装置中存储的密码数据的存储位置和/或存储顺序进行资源化设计来实现改进的安全功能，以防止未经授权的密码获取。 存储装置确定通过验证密码是否允许重写和/或读取数据，该存储装置包括多个部分存储区域，该多个部分存储区域存储多个部分位串，该多个部分位串包括 密码，并且其中所述多个部分存储器区域在存储单元阵列中彼此分开。

公开(公告)号：US20090049253A1

公开(公告)日：2009-02-19

申请号：US12012390

申请日：2008-02-01

申请人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

发明人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

IPC分类号： G06F12/00

CPC分类号： G11C16/22

摘要： The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region

摘要翻译： 本发明提供半导体器件和控制半导体器件的方法，该半导体器件包括包括非易失性存储器单元的存储区域; 程序禁止信息单元，程序禁止信息单元存储要用于确定是否禁止或允许在对应于程序禁止信息单元的多个存储器区域中进行编程的程序禁止信息; 第一禁止信息控制电路，禁止将程序禁止信息从程序禁止状态改变为允许相对于存储区域的状态的程序，所述存储区域是所述多个对应的存储区域中的一个，基于第一禁止信息 用于确定是否禁止将程序禁止信息从程序禁止状态改变为相对于对应的存储区域的程序允许状态; 以及第二禁止信息控制电路，其基于第二禁止信息来禁止程序禁止信息从允许状态到相对于存储区域的程序禁止状态的程序的改变，所述第二禁止信息控制电路用于确定是否禁止改变 程序禁止信息从允许状态到相对于对应的存储器区域的程序禁止状态的程序

公开(公告)号：US6097658A

公开(公告)日：2000-08-01

申请号：US189148

申请日：1998-11-10

申请人： Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元， 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US08443131B2

公开(公告)日：2013-05-14

申请号：US11259874

申请日：2005-10-26

申请人： Mitsuhiro Nagao ,  Kenta Kato

发明人： Mitsuhiro Nagao ,  Kenta Kato

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C11/34 ,  G11C16/04 ,  G11C7/10

CPC分类号： G11C7/20 ,  G11C7/24 ,  G11C8/08 ,  G11C11/417 ,  G11C16/20 ,  G11C16/225 ,  G11C29/028 ,  G11C2029/4402

摘要： Operational information read out by a read-out sense amplifier (19) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section (21) having a SRAM configuration and the second volatile memory section (23) configured with latch circuits, both sections respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section (21) in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (23). Thus, the operational information is available in response to attributes of the operational information.

摘要翻译： 由读出放大器（19）读出的操作信息经由数据线DB传送到易失性存储器部分。 易失性存储器部分配置有具有SRAM配置的易失性存储器部分（21）和配置有锁存电路的第二易失性存储器部分（23），两个部分分别与数据线DB并联连接。 可以根据写保护信息的操作状态和由字线WLWP选择的存储在非易失性存储单元MC中的其他信息提供的操作信息相对于第一易失性存储器被写入和读出 部分（21）响应于与操作信息相关联的识别信息。 必须经常访问的操作信息被写入第二易失性存储器部分（23）。 因此，响应于操作信息的属性，操作信息可用。

公开(公告)号：US08219743B2

公开(公告)日：2012-07-10

申请号：US13052486

申请日：2011-03-21

申请人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

发明人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

IPC分类号： G06F12/00

CPC分类号： G11C16/22

摘要： The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions; program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in the memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state with respect to a memory region based on first prohibition information; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region based on second prohibition information with respect to the corresponding memory region.

摘要翻译： 本发明提供半导体器件和控制半导体器件的方法，该半导体器件包括存储区域; 程序禁止信息单元存储用于确定是否禁止或允许对应于程序禁止信息单元的存储器区域中的编程的程序禁止信息; 第一禁止信息控制电路，基于第一禁止信息禁止程序禁止信息相对于存储区域的程序禁止状态的改变; 以及第二禁止信息控制电路，其基于相对于存储区域的第二禁止信息，禁止将程序禁止信息从允许状态改变为相对于存储区域的程序禁止状态的程序。

公开(公告)号：US07565477B2

公开(公告)日：2009-07-21

申请号：US11644031

申请日：2006-12-22

申请人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

发明人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

IPC分类号： G06F12/00

CPC分类号： G06F12/1433 ,  G06F2212/2022

摘要： A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.

摘要翻译： 半导体器件包括：包括非易失性存储单元的存储器区域; 禁用与存储器区域相对应的信息存储单元，每个禁用信息存储单元存储指示是否在每个对应的存储器区域中禁用或启用编程的第一程序禁用信息; 程序禁用信息选择电路，当根据集合程序禁止信息指示是否编程是否被编程时，输出第二程序禁用信息以禁止在对应的存储器区域中的编程，而不管第一程序禁用信息 在存储区域中集中禁止，程序禁止信息选择电路输出第一程序禁用信息作为编程时的第二程序禁用信息不被集中禁用; 以及程序控制电路，其根据第二程序禁止信息禁止或使得能够在对应的存储器区域中进行编程。

公开(公告)号：US20080155180A1

公开(公告)日：2008-06-26

申请号：US11644031

申请日：2006-12-22

申请人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

发明人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

IPC分类号： G06F12/02

CPC分类号： G06F12/1433 ,  G06F2212/2022

摘要： A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.

摘要翻译： 半导体器件包括：包括非易失性存储单元的存储器区域; 禁用与存储器区域相对应的信息存储单元，每个禁用信息存储单元存储指示是否在每个对应的存储器区域中禁用或启用编程的第一程序禁用信息; 程序禁用信息选择电路，当根据集合程序禁止信息指示是否编程是否被编程时，输出第二程序禁用信息以禁止在对应的存储器区域中的编程，而不管第一程序禁用信息 在存储区域中集中禁止，程序禁止信息选择电路输出第一程序禁用信息作为编程时的第二程序禁用信息不被集中禁用; 以及程序控制电路，其根据第二程序禁止信息禁止或使得能够在对应的存储器区域中进行编程。