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    Shoe insole
    3.
    发明申请
    Shoe insole 审中-公开
    鞋垫

    公开(公告)号：US20050060910A1

    公开(公告)日：2005-03-24

    申请号：US10499459

    申请日：2002-12-25

    申请人： Yasushi Kaneda ,  Minoru Morimoto

    发明人： Yasushi Kaneda ,  Minoru Morimoto

    IPC分类号： A43B3/26 ,  A43B17/00 ,  A43B13/38 ,  A43B23/00

    CPC分类号： A43B17/003 ,  A43B1/009 ,  A43B3/26

    摘要： An insole easy to wash and excellent in adhesiveness to the sole of a shoe is provided. An insole produced by punching a piece of the shape of a sole of a shoe or the shape of the leading terminal of a sole of a shoe out of a thermoplastic elastomer by the injection molding technique.

    摘要翻译： 提供了容易洗涤的鞋垫和与鞋底的粘合性优异。 通过注射成型技术将热塑性弹性体中的一块鞋底的形状或鞋底的前端的形状冲出热塑性弹性体而制成的内底。

    Digital signal processor with on board program having arithmetic instructions and direct memory access instructions for controlling direct memory access thereof
    4.
    发明授权
    Digital signal processor with on board program having arithmetic instructions and direct memory access instructions for controlling direct memory access thereof 失效
    具有车载程序的数字信号处理器具有用于控制其直接存储器访问的算术指令和直接存储器访问指令

    公开(公告)号：US5765025A

    公开(公告)日：1998-06-09

    申请号：US542729

    申请日：1995-10-13

    申请人： Minoru Morimoto ,  Yoshiji Yoshida

    发明人： Minoru Morimoto ,  Yoshiji Yoshida

    IPC分类号： G06F9/34 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3824 ,  G06F9/34

    摘要： There is provided a method of controlling direct memory access for a digital signal-processing system. Direct memory access (DMA) instructions for executing data transfer by direct memory access between a data memory storing data and an external device are provided in a program, together with arithmetic processing instructions for executing arithmetic processing. The data transfer by the direct memory access is executed between the data memory and the external device according to each of the DMA instructions which has been decoded during execution of the program, upon decoding thereof. There is also provided a digital signal-processing system which causes data transfer by direct memory access to begin. An arithmetic operation device of the system arithmetically processes data read out from a data memory of the same under the control of decoded instructions of a program. The program contains DMA instructions for executing the data transfer by the direct memory access as well as arithmetic processing instructions. The data transfer by the direct memory access between an external device and the data memory is started when each of the DMA instructions is decoded during execution of the program.

    摘要翻译： 提供了一种控制数字信号处理系统的直接存储器访问的方法。 与存储数据和外部设备的数据存储器之间的直接存储器访问执行数据传送的直接存储器访问（DMA）指令与用于执行算术处理的算术处理指令一起被提供在程序中。 通过直接存储器访问的数据传输，在数据存储器和外部设备之间根据在程序执行期间被解码的每个DMA指令执行。 还提供了一种数字信号处理系统，其通过直接存储器访问来开始数据传输。 该系统的算术运算装置在程序的解码指令的控制下，对从数据存储器读出的数据进行算术处理。 该程序包含用于通过直接存储器访问执行数据传输的DMA指令以及算术处理指令。 当在程序执行期间对每个DMA指令进行解码时，开始在外部设备与数据存储器之间进行直接存储器访问的数据传输。

    Method of filling polygonal region in video display system
    5.
    发明授权
    Method of filling polygonal region in video display system 失效
    在视频显示系统中填充多边形区域的方法

    公开(公告)号：US4914729A

    公开(公告)日：1990-04-03

    申请号：US16071

    申请日：1987-02-18

    申请人： Mutsuhiro Omori ,  Hidefumi Terada ,  Minoru Morimoto

    发明人： Mutsuhiro Omori ,  Hidefumi Terada ,  Minoru Morimoto

    IPC分类号： G09G5/36 ,  G06T11/40

    CPC分类号： G06T11/40

    摘要： A method of filling a polygonal region enables a polygon of any shape to be filled with pixels with a simple algorithm. A display memory area and a working area each having a plurality of addresses correponding to all the pixels on a display screen are provided. A minimum rectangular area including the polygon is determined in accordance with all the polygon vertices, and the minimum rectangular area within the working area is cleared. A straight line (or an edge) connecting each pair of adjoining vertices of the polygon is described to the display memory area with predetermined values. The edges are also described to the working area but in accordance with three rules. Under Rule 1, when a constituent dot of the edge is described to the corresponding address, the data in the address is inverted. Under Rule 2, a start constituent dot of each edge is described only when the edge to be described has an inclination different in polarity from the precedingly described edge. Under Rule 3, the constituent dot of each edge is described only when the constituent dot is shifted in the vertical direction. Then, the rectangular area in the working area is scanned to detect dots in the state of "1" for each scanning line and to number the detected dots. Finally, addresses of the display memory area corresponding to each interval from the odd-numbered detected dot to the even-numbered detected dot are filled with predetermined values.

    摘要翻译： 填充多边形区域的方法能够以简单的算法将任何形状的多边形填充到像素中。 提供显示存储区域和工作区域，每个显示存储区域和工作区域具有与显示屏幕上的所有像素对应的多个地址。 根据所有多边形顶点确定包括多边形的最小矩形区域，并且清除工作区域内的最小矩形区域。 将连接多边形的每对相邻顶点的直线（或边缘）以预定值描述到显示存储区域。 边缘也被描述到工作区域，但是根据三个规则。 根据规则1，当边缘的组成点被描述为相应的地址时，地址中的数据被反转。 在规则2中，仅当要描述的边缘具有与前述边缘不同的极性的倾斜度时才描述每个边缘的起始构成点。 在规则3下，每个边缘的组成点仅在组成点在垂直方向上移位时才被描述。 然后，对每个扫描线扫描工作区域中的矩形区域以检测处于“1”的状态的点，并对检测到的点进行编号。 最后，将从奇数检测点到偶数检测点的每个间隔对应的显示存储区的地址用预定值填充。

    Video display control system for moving display images
    6.
    发明授权
    Video display control system for moving display images 失效
    用于移动显示图像的视频显示控制系统

    公开(公告)号：US4897636A

    公开(公告)日：1990-01-30

    申请号：US139170

    申请日：1987-12-21

    申请人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

    发明人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

    IPC分类号： G06T1/60 ,  G09G5/02 ,  G09G5/393

    CPC分类号： G09G5/393 ,  G06T1/60 ,  G09G5/026

    摘要： A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area. A reading circuit reads the display data in the first memory locations in accordance with the first address data, while a writing circuit writes the read display data into the second memory locations in accordance with the second address data. This video display control system further includes another reading circuit and an operation circuit. This reading circuit reads the display data in the second memory locations and feeds the read display data to the operation circuit which effects an operation such as a logical operation or a transparency processing on each pair of the display data read from the first and second memory locations.

    摘要翻译： 视频显示控制系统能够将静止图像的一部分从第一显示区域移动到屏幕上的第二显示区域。 视频显示控制系统包括由多个存储位置组成的存储器，用于存储表示屏幕上显示元素的图像的多个显示数据。 第一和第二寄存器保持表示第一和第二显示区域的第一和第二区域数据，并且地址数据生成器从这些区域数据生成第一和第二地址数据，第一地址数据指示存储对应于第一和第二显示区域的显示数据的存储单元 显示区域，第二地址数据指示存储对应于第二显示区域的显示数据的第二存储单元。 读取电路根据第一地址数据读取第一存储器位置中的显示数据，而写入电路根据第二地址数据将读取的显示数据写入第二存储器位置。 该视频显示控制系统还包括另一读取电路和操作电路。 该读取电路读取第二存储器位置中的显示数据并将读取的显示数据馈送到对从第一和第二存储器位置读取的每对显示数据执行诸如逻辑操作或透明度处理的操作的操作电路 。

    Video display control system
    7.
    发明授权
    Video display control system 失效
    视频显示控制系统

    公开(公告)号：US4731742A

    公开(公告)日：1988-03-15

    申请号：US712253

    申请日：1985-03-15

    申请人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

    发明人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

    IPC分类号： G09G5/02 ,  G09G5/393 ,  G06F3/153

    CPC分类号： G09G5/393 ,  G09G5/02

    摘要： A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM. Through this second register, the memory accessing circuit performs a memory accessing operation such as a transfer of color code between the external device and the VRAM, whereby color painting on a display area such as a rectangular area, dot and a line can easily be achieved. The VDP further comprises an operation circuit for effecting a certain operation on a color code in the second register and a color code in the VRAM and generating a new color code in accordance with the operation result. The operation-related color change on a display area can be achieved by storing the new color code in a corresponding memory location of the VRAM.

    摘要翻译： 一种用于在视频显示单元的屏幕上显示视频图像的视频显示控制系统。 该视频显示控制系统基本上包括VRAM（视频RAM）和视频显示处理器（VDP）。 VRAM具有与屏幕上的显示元素相对应的存储器位置。 VDP包括用于接收区域信息的第一寄存器，用于识别屏幕上的显示区域;地址发生器，用于根据区域信息产生对应于显示区域的存储位置的地址;以及存储器访问电路，用于访问具有 地址。 因此，通过该VDP的存储器访问操作不需要中央处理单元的复杂支持。 VDP还包括用于存储从外部设备提供或从VRAM读取的颜色代码的第二寄存器。 通过该第二寄存器，存储器访问电路执行存储器访问操作，例如外部设备和VRAM之间的颜色代码的传送，由此可以容易地实现诸如矩形区域，点和行的显示区域上的彩色绘画 。 VDP还包括用于对第二寄存器中的颜色代码进行某种操作的操作电路和VRAM中的颜色代码，并根据操作结果生成新的颜色代码。 可以通过将新的颜色代码存储在VRAM的对应的存储器位置中来实现显示区域上的与操作相关的颜色变化。

    Video display control system
    8.
    发明授权
    Video display control system 失效
    视频显示控制系统

    公开(公告)号：US4628467A

    公开(公告)日：1986-12-09

    申请号：US735370

    申请日：1985-05-17

    申请人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

    发明人： Kazuhiko Nishi ,  Takatoshi Ishii ,  Ryozo Yamashita ,  Shigemitsu Yamaoka ,  Takatoshi Okumura ,  Minoru Morimoto

    IPC分类号： G06F3/153 ,  G06T1/60 ,  G06T11/00 ,  G09G5/391 ,  G06F15/62 ,  G09G1/02 ,  G09G1/28

    CPC分类号： G06T1/60 ,  G09G5/391

    摘要： A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus. The VRAM interface first outputs row address data together with a row address strobe signal RAS and then outputs column address data together with two column address strobe signals CAS0 and CAS1 which are rendered active in sequence and supplied to the first and second dynamic RAMs, respectively.

    摘要翻译： 视频显示控制系统包括能够以极高速度访问视频RAM（VRAM）的视频显示处理器（VDP）。 该系统中使用的VRAM包括第一和第二动态RAM，每个具有地址输入端，行地址数据和列地址数据被提供给地址输入端，行地址选通输入端，列地址选通输入端和数据输入/输出 终奌站。 行地址数据被锁存在施加到行地址选通输入端的行地址选通信号的前沿，而列地址数据被锁存在施加到列地址选通输入端的列地址选通信号的前沿 。 当锁存行和列地址数据时，建立对每个动态RAM的地址的访问。 VDP包括用于控制通过公共地址总线连接到RAM的第一和第二动态RAM的访问的VRAM接口。 VRAM接口首先将行地址数据与行地址选通信号和上拉和下拉一起输出，然后将列地址数据与两个列地址选通信号和上拉和C和＆amp;上拉和C依次输出并提供给第一和第二动态RAM ， 分别。