公开(公告)号：US08575739B2

公开(公告)日：2013-11-05

申请号：US13102291

申请日：2011-05-06

Applicant: Suresh Upadhyayula ,  Ming Hsun Lee ,  Hem Takiar

Inventor： Suresh Upadhyayula ,  Ming Hsun Lee ,  Hem Takiar

IPC: H01L23/02

CPC classification number: H01L23/4951 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted.

Abstract translation: 公开了一种半导体封装，其包括引线框架，存储器管芯和控制器管芯，其中一个或多个被定制以促进存储器和控制器管芯接合焊盘经由引线框架将电连接到主机设备的接触焊盘。 通过定制引线框，存储管芯和控制器管芯中的一个或多个，可以省略通常需要将半导体封装中的管芯与主机器件连接的插入层。

公开(公告)号：US07728411B2

公开(公告)日：2010-06-01

申请号：US11354441

申请日：2006-02-15

Applicant: Ming Hsun Lee ,  Cheemen Yu ,  Hem Takiar

Inventor： Ming Hsun Lee ,  Cheemen Yu ,  Hem Takiar

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H01L23/4951 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.

Abstract translation: 公开了制造半导体封装的方法和由此形成的半导体封装。 半导体封装可以包括一个或多个半导体管芯，其具有沿着单侧的管芯附接焊盘。 引线框架可以包括多个细长的电引线，从引线框架的第一侧延伸到管芯下方，并且沿着模具的单个边缘终止在与引线框架相邻的接合焊盘的第二侧。 引线框架还可以包括细长引线上的电介质间隔层。 使用间隔层从细长引线间隔半导体管芯减小了由此形成的半导体封装的寄生电容和/或电感。

公开(公告)号：US20090004783A1

公开(公告)日：2009-01-01

申请号：US11769140

申请日：2007-06-27

Applicant: Ming Hsun Lee ,  Cheemen Yu

Inventor： Ming Hsun Lee ,  Cheemen Yu

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L23/49555 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages.

Abstract translation: 公开了一种半导体封装组件，其包括一对堆叠的基于引线框的半导体封装。 第一包装被封装在模具化合物中，使得电引线从封装的侧面附近散布在封装的底表面附近。 第一封装可以堆叠在第二封装顶部，通过将第一封装的暴露引线与第二封装的裸露引线对准，并将两个封装的相应引线固定在一起。 引线朝向第一封装的底部的垂直偏移提供与第二封装的引线更大的重叠，从而允许相应封装的引线的牢固结合。

公开(公告)号：US20090001529A1

公开(公告)日：2009-01-01

申请号：US11769149

申请日：2007-06-27

Applicant: Ming Hsun Lee ,  Cheemen Yu

Inventor： Ming Hsun Lee ,  Cheemen Yu

IPC: H01L23/02

CPC classification number: H01L23/49555 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages.

Abstract translation: 公开了一种半导体封装组件，其包括一对堆叠的基于引线框的半导体封装。 第一包装被封装在模具化合物中，使得电引线从封装的侧面附近散布在封装的底表面附近。 第一封装可以堆叠在第二封装顶部，通过将第一封装的暴露引线与第二封装的裸露引线对准，并将两个封装的相应引线固定在一起。 引线朝向第一封装的底部的垂直偏移提供与第二封装的引线更大的重叠，从而允许相应封装的引线的牢固结合。

公开(公告)号：US06861736B2

公开(公告)日：2005-03-01

申请号：US10465076

申请日：2003-06-18

Applicant: Ming-Hsun Lee ,  Ho-Yi Tsai

Inventor： Ming-Hsun Lee ,  Ho-Yi Tsai

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/28

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A leadframe-based semiconductor package is proposed for the packaging of a semiconductor device, such as a multi-media card (MMC) chipset. The proposed semiconductor package is characterized by the use of a leadframe, rather than BT substrate or film, as the chip carrier for MMC chipset. The leadframe includes a supporting bar; a chip-supporting structure arranged at a downset position in relation to the supporting bar; and a plurality of leads, each lead including an outer-lead portion and an inner-lead portion; wherein the outer-lead portion is levelly linked to the supporting bar, while the inner-lead portion is arranged beside the chip-supporting structure and linked to the outer-lead portion via an intermediate-lead portion. The leadframe can be either the type having die pad or the type having no die pad. In the case of the type having die pad, a semiconductor chip is mounted on the die pad; and in the case of the type having no die pad, one or more semiconductor chips are mounted over an elongated part of the inner-lead portions of the leads. The use of leadframe allows the MMC package to be manufactured without having to include a lidding process, so that the MMC manufacture can be carried out in a less complex and more cost-effective manner.

Abstract translation: 提出了一种用于半导体器件（例如多媒体卡（MMC）芯片组）的封装的基于引线框的半导体封装。 所提出的半导体封装的特征在于使用引线框架而不是BT基板或薄膜作为用于MMC芯片组的芯片载体。 引线框架包括支撑杆; 芯片支撑结构相对于所述支撑杆布置在折叠位置; 以及多个引线，每个引线包括外部引线部分和内部引线部分; 其中，所述外引线部分与所述支撑杆平齐地连接，而所述内引线部分布置在所述芯片支撑结构旁边，并且经由中间引线部分连接到所述外引线部分。 引线框架可以是具有管芯焊盘的类型或者没有管芯焊盘的类型。 在具有管芯焊盘的类型的情况下，半导体芯片安装在管芯焊盘上; 并且在没有管芯焊盘的情况下，在引线的内引线部分的细长部分上安装一个或多个半导体芯片。 引线框的使用允许制造MMC封装，而不必包括封装工艺，以便MMC制造可以以较不复杂和更具成本效益的方式进行。

公开(公告)号：US09909305B2

公开(公告)日：2018-03-06

申请号：US15620887

申请日：2017-06-13

Applicant: Ming-Hsun Lee

Inventor： Ming-Hsun Lee ,  Chia-Ching Lee ,  Dong-Ying Su

IPC: E04B2/60 ,  E04B2/56 ,  E04B1/94 ,  E04C3/32

CPC classification number: E04B2/60 ,  E04B1/7675 ,  E04B1/942 ,  E04B2/562 ,  E04B2/7414 ,  E04B2/7457 ,  E04B2/7854 ,  E04B9/065 ,  E04B9/22 ,  E04B2103/06 ,  E04C3/02 ,  E04C3/32 ,  E04H9/021

Abstract: A composite wall assembly has an auxiliary wall and an inner wall. The auxiliary wall has a hollow space and a first supporting pillar having multiple first through holes. The inner wall is attached to the auxiliary wall and forms a depositing space. The inner wall has a first wall member, a second wall member, and a second supporting pillar having multiple second through holes. The depositing space is formed between the first wall member and the second wall member. The auxiliary wall provides a cushion effect and is not damaged easily in the earthquake for protecting the pipelines in the hollow space. The interior ambient temperature of the building is lowered by the hollow space of the auxiliary wall.

公开(公告)号：US06603196B2

公开(公告)日：2003-08-05

申请号：US09820135

申请日：2001-03-28

Applicant: Ming-Hsun Lee ,  Ho-Yi Tsai

Inventor： Ming-Hsun Lee ,  Ho-Yi Tsai

IPC: H01L23495

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A leadframe-based semiconductor package is proposed for the packaging of a semiconductor device, such as a multi-media card (MMC) chipset. The proposed semiconductor package is characterized by the use of a leadframe, rather than BT substrate or film, as the chip carrier for MMC chipset. The leadframe includes a supporting bar, a chip-supporting structure arranged at a downset position in relation to the supporting bar; and a plurality of leads, each lead including an outer-lead portion and an inner-lead portion; wherein the outer-lead portion is levelly linked to the supporting bar, while the inner-lead portion is arranged beside the chip-supporting structure and linked to the outer-lead portion via an intermediate-lead portion. The leadframe can be either the type having die pad or the type having no die pad. In the case of the type having die pad, a semiconductor chip is mounted on the die pad; and in the case of the type having no die pad, one or more semiconductor chips are mounted over an elongated part of the inner-lead portions of the leads. The use of leadframe allows the MMC package to be manufactured without having to include a lidding process, so that the MMC manufacture can be carried out in a less complex and more cost-effective manner.

公开(公告)号：US08097495B2

公开(公告)日：2012-01-17

申请号：US12060418

申请日：2008-04-01

Applicant: Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

Inventor： Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

IPC: H01L21/50 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/4951 ,  H01L23/49551 ,  H01L23/49558 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.

Abstract translation: 公开了一种用于半导体封装的引线框架，其包括从引线框架的一侧延伸到引线框架的相反侧的电引线，其中可以在引线框架的第二侧与半导体管芯进行电连接。 半导体管芯可以被支撑在引导框架上延伸的引线上。 封装还可以包括固定到电引线上的间隔层，以强化半导体封装并防止在封装成型期间电引线的暴露。

公开(公告)号：US20170362823A1

公开(公告)日：2017-12-21

申请号：US15620887

申请日：2017-06-13

Applicant: Ming-Hsun Lee

Inventor： Ming-Hsun Lee ,  Chia-Ching Lee ,  Dong-Ying Su

IPC: E04B2/60 ,  E04B1/94 ,  E04B2/56 ,  E04C3/32

CPC classification number: E04B2/60 ,  E04B1/7675 ,  E04B1/942 ,  E04B2/562 ,  E04B2/7414 ,  E04B2/7457 ,  E04B2/7854 ,  E04B9/065 ,  E04B9/22 ,  E04B2103/06 ,  E04C3/02 ,  E04C3/32 ,  E04H9/021

Abstract: A composite wall assembly has an auxiliary wall and an inner wall. The auxiliary wall has a hollow space and a first supporting pillar having multiple first through holes. The inner wall is attached to the auxiliary wall and forms a depositing space. The inner wall has a first wall member, a second wall member, and a second supporting pillar having multiple second through holes. The depositing space is formed between the first wall member and the second wall member. The auxiliary wall provides a cushion effect and is not damaged easily in the earthquake for protecting the pipelines in the hollow space. The interior ambient temperature of the building is lowered by the hollow space of the auxiliary wall.

公开(公告)号：US20090166820A1

公开(公告)日：2009-07-02

申请号：US11965709

申请日：2007-12-27

Applicant: Hem Takiar ,  Shrikar Bhagath ,  Ming Hsun Lee ,  Bonnie Ming-Yan Chan

Inventor： Hem Takiar ,  Shrikar Bhagath ,  Ming Hsun Lee ,  Bonnie Ming-Yan Chan

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/4951 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/97 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby are disclosed. An entire row or column of leadframes gets encapsulated together. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages, which allows the internal leads of each leadframe and the semiconductor die coupled thereto to be lengthened.

Abstract translation: 公开了一种从包括多重封装的引线框封装的条带制造半导体引线框封装的方法，以及由此形成的引线框封装。 引线框的整个行或列被封装在一起。 封装整个行或列减少相邻引线框封装之间的保留区域，这允许每个引线框架的内部引线和与其耦合的半导体管芯延长。