公开(公告)号：US20120237930A1

公开(公告)日：2012-09-20

申请号：US13417522

申请日：2012-03-12

Applicant: Hiro Nitta ,  Mike Farrell ,  Wenjun Zhang ,  Tom Grogan

Inventor： Hiro Nitta ,  Mike Farrell ,  Wenjun Zhang ,  Tom Grogan

IPC: G01N33/53

CPC classification number: C12Q1/6841 ,  C12Q1/6827 ,  C12Q2525/185 ,  C12Q2539/115 ,  C12Q2565/102 ,  C12Q2543/101

Abstract: The present disclosure relates to systems and methods for analyzing chromosomal translocations, and in particular to analysis of chromosomal translocation by in situ hybridization.

Abstract translation: 本公开涉及用于分析染色体易位的系统和方法，特别是通过原位杂交分析染色体易位。

公开(公告)号：US09562259B2

公开(公告)日：2017-02-07

申请号：US13417522

申请日：2012-03-12

Applicant: Hiro Nitta ,  Mike Farrell ,  Wenjun Zhang ,  Tom Grogan

Inventor： Hiro Nitta ,  Mike Farrell ,  Wenjun Zhang ,  Tom Grogan

IPC: C12Q1/68 ,  G01N33/53

CPC classification number: C12Q1/6841 ,  C12Q1/6827 ,  C12Q2525/185 ,  C12Q2539/115 ,  C12Q2565/102 ,  C12Q2543/101

Abstract: The present disclosure relates to systems and methods for analyzing chromosomal translocations, and in particular to analysis of chromosomal translocation by in situ hybridization.

Abstract translation: 本公开涉及用于分析染色体易位的系统和方法，特别是通过原位杂交分析染色体易位。

公开(公告)号：US06972998B1

公开(公告)日：2005-12-06

申请号：US10774904

申请日：2004-02-09

Applicant: David Gibson ,  Angus David Starr MacAdam ,  Mike Farrell

Inventor： David Gibson ,  Angus David Starr MacAdam ,  Mike Farrell

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/4096 ,  G11C29/02

CPC classification number: G11C29/028 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/50012

Abstract: An integrated circuit memory device includes a memory, a read control circuit operatively associated with the memory and configured to produce data from the memory responsive to an externally-applied input clock signal, and an output latch configured to transfer data at an input thereof to an output pad of the memory device responsive to an externally-applied output clock signal. The device further includes a clock domain alignment circuit configured to receive the data produced by the memory and to responsively provide the data at the input of the output latch based on relative timing of the input clock signal and the output clock signal.

Abstract translation: 集成电路存储器件包括存储器，与存储器可操作地相关联并被配置为响应于外部施加的输入时钟信号从存储器产生数据的读取控制电路，以及输出锁存器，被配置为将数据在其输入处传送到 存储器件的输出焊盘响应外部施加的输出时钟信号。 该器件还包括时钟域对准电路，其被配置为接收存储器产生的数据，并且基于输入时钟信号和输出时钟信号的相对定时响应地在输出锁存器的输入处提供数据。

公开(公告)号：US07046058B1

公开(公告)日：2006-05-16

申请号：US10671305

申请日：2003-09-24

Applicant: Al Fang ,  Mike Farrell ,  Brian Butka

Inventor： Al Fang ,  Mike Farrell ,  Brian Butka

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0818

Abstract: A delay-locked loop (DLL) circuit includes a phase interpolator circuit and variable delay circuit coupled in cascade and operative to generate an output clock signal that is delayed with respect to a reference clock signal responsive to respective first and second control signals applied to the phase interpolator and the variable delay circuit. The DLL circuit further includes a phase control circuit that generates the first and second control signals responsive to the output clock signal and the reference clock signal. The variable delay circuit may provide a coarser resolution than the phase interpolator circuit, for example, the variable delay circuit may include a tapped delay chain circuit configured to provide step changes in delay responsive to the second control signal. The phase control circuit may be operative to cause the phase interpolator circuit to shift from one extreme of a delay range thereof towards another extreme of the delay range concurrent with a step change in delay through the variable delay circuit to thereby limit overcompensation.

Abstract translation: 延迟锁定环路（DLL）电路包括相位内插器电路和可变延迟电路，其可级联耦合并且可操作以产生相对于参考时钟信号延迟的输出时钟信号，所述输出时钟信号响应于施加到所述第一和第二控制信号的相应的第一和第二控制信号 相位内插器和可变延迟电路。 该DLL电路还包括相位控制电路，该相位控制电路根据输出时钟信号和参考时钟信号产生第一和第二控制信号。 可变延迟电路可以提供比相位内插器电路更粗的分辨率，例如，可变延迟电路可以包括被配置为响应于第二控制信号提供延迟的延迟阶跃变化的抽头延迟链电路。 相位控制电路可操作以使相位内插器电路从其延迟范围的一个极端移向延迟范围的另一极端，并通过可变延迟电路与延迟的阶跃变化同步，从而限制过补偿。