Abstract:
A method and apparatus to encoding or decoding an audio signal is provided. In the method and apparatus, a noise-floor level to use in encoding or decoding a high frequency signal is updated according to the degree of a voiced or unvoiced sound included in the signal.
Abstract:
A method of encoding an audio signal, where signals including two or more channel signals are downmixed to a mono signal, the mono signal is divided into a low-frequency signal and a high-frequency signal, the low-frequency signal is encoded through algebraic code excited linear prediction (ACELP) or transform coded excitation (TCX), and the high-frequency signal is encoded using the low-frequency signal. A method of decoding of an audio signal, a low-frequency signal encoded through ACELP or TCX is decoded, a high-frequency signal is decoded using the low-frequency signal, the low-frequency signal and the high-frequency signal are combined to generate a mono signal, and the mono signal is upmixed by decoding spatial parameters regarding signals including two or more channel signals.
Abstract:
Disclosed is an apparatus for encoding and/or decoding an audio signal having a variable bit rate (VBR). A target bit rate is determined in accordance with characteristics of an audio signal, and a weighted linear predictive transform coding is performed in accordance with the determined target bit rate.
Abstract:
A method and apparatus of effectively encoding and decoding a high-frequency signal of a multi-channel audio are provided. A multi-channel audio decoding apparatus may down-mix a multi-channel audio input signal, expand a number of channels of the down-mixed signal, select at least one of the expanded channel signal, extract a parameter indicating a characteristic relation between the selected signal and the multi-channel audio input signal, and encode the down-mixed signal and the extracted parameter.
Abstract:
A resist underlayer composition and a method of manufacturing a semiconductor integrated circuit device, the resist underlayer composition including a solvent and an organosilane-based polymer, the organosilane-based polymer being a polymerization product of at least one first compound represented Chemical Formulae 1 to 3 and at least one second compound represented by Chemical Formulae 4 and 5.
Abstract:
A semiconductor device includes a high voltage first conduction type well in a semiconductor substrate, a second conduction type body in the high voltage first conduction type well, a source region in the second conduction type body, a trench in the high voltage first conduction type well, a first isolation oxide, an impurity doped polysilicon film, and a second isolation oxide stacked in the trench in succession, a drain region in the high voltage first conduction type well on one side of the trench, and a polygate on and/or over the high voltage first conduction type well.
Abstract:
A hardmask composition for processing a resist underlayer film includes a solvent and an organosilane polymer, wherein the organosilane polymer is represented by Formula 6: In Formula 6, R is methyl or ethyl, R′ is substituted or unsubstituted cyclic or acyclic alkyl, Ar is an aromatic ring-containing functional group, x, y and z satisfy the relations x+y=4, 0.4≦x≦4, 0≦y≦3.6, and 4×10−4≦z≦1, and n is from about 3 to about 500.
Abstract translation:用于加工抗蚀剂下层膜的硬掩模组合物包括溶剂和有机硅烷聚合物,其中有机硅烷聚合物由式6表示:在式6中,R是甲基或乙基,R'是取代或未取代的环状或无环烷基,Ar是 含芳环的官能团x,y和z满足x + y = 4,0.4 <= x <= 4,0 <= y <= 3.6和4×10-4 <= z <1的关系,以及 n为约3至约500。
Abstract:
A method for fabricating a semiconductor device having a capacitor is provided. The method includes forming an isolation layer on a substrate on which a capacitor region and a transistor region are defined, forming a trench in the isolation layer, sequentially forming a first polysilicon layer, a dielectric layer, and a second polysilicon layer on an entire surface of the substrate including the trench, forming a capacitor in the trench by performing a chemical mechanical polishing process until an upper surface of the isolation layer is exposed, forming a first photoresist pattern to expose the transistor region, removing the second polysilicon layer and the dielectric layer using the first photoresist pattern as a mask, forming a second photoresist pattern in the transistor region, and forming a gate electrode by selectively removing the first polysilicon layer in the transistor region using the second photoresist pattern as a mask.
Abstract:
A semiconductor memory device includes a repeater located at a global input/output (GIO) line. The repeater buffers and transmits data between a data pad and a plurality of banks. The semiconductor memory device also includes a repeater control unit adapted to control the operation of the repeater in response to a read/write command associated with one of the plurality of banks. When a read or write operation is performed for the banks located farthest from the data pads, the repeater on the GIO line buffers the GIO signal, and thereby reduces the load of the GIO line, decreases the delay of the GIO signal, and improves the slope of the GIO signal. As a result, the semiconductor memory device is useful during high speed operations.