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    Integrated circuit test optimization using adaptive test pattern sampling algorithm
    1.
    发明授权
    Integrated circuit test optimization using adaptive test pattern sampling algorithm 失效
    使用自适应测试模式采样算法的集成电路测试优化

    公开(公告)号：US08689066B2

    公开(公告)日：2014-04-01

    申请号：US13172179

    申请日：2011-06-29

    申请人： Matthew S. Grady ,  Mark C. Johnson ,  Bradley D. Pepper ,  Dean G. Percy ,  Joseph C. Pranys

    发明人： Matthew S. Grady ,  Mark C. Johnson ,  Bradley D. Pepper ,  Dean G. Percy ,  Joseph C. Pranys

    IPC分类号： G01R31/28

    CPC分类号： G06F11/263 ,  G01R31/31835

    摘要： A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.

    摘要翻译： 实现集成电路设备测试的方法包括使用全套测试模式来执行第一组芯片的基线测试，以及对于被识别为故障的芯片，确定全集中每个测试模式的得分。 该分数表示测试图案相对于其他测试图案唯一地识别故障芯片的能力。 在基线测试之后，使用由基线测试确定的具有最高平均分数的测试模式的一组减少的集合来执行第二组芯片的简化测试。 在精简测试之后，使用完整的测试模式进行第三组芯片的全面测试，并更新每种模式的平均分数。 进一步的测试在简化的测试和对另外一组芯片的完整测试之间进行了交替。

    INTEGRATED CIRCUIT TEST OPTIMIZATION USING ADAPTIVE TEST PATTERN SAMPLING ALGORITHM
    2.
    发明申请
    INTEGRATED CIRCUIT TEST OPTIMIZATION USING ADAPTIVE TEST PATTERN SAMPLING ALGORITHM 失效
    使用自适应测试图形采样算法的集成电路测试优化

    公开(公告)号：US20130007546A1

    公开(公告)日：2013-01-03

    申请号：US13172179

    申请日：2011-06-29

    申请人： Matthew S. Grady ,  Mark C. Johnson ,  Bradley D. Pepper ,  Dean G. Percy ,  Joseph C. Pranys

    发明人： Matthew S. Grady ,  Mark C. Johnson ,  Bradley D. Pepper ,  Dean G. Percy ,  Joseph C. Pranys

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G06F11/263 ,  G01R31/31835

    摘要： A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.

    摘要翻译： 实现集成电路设备测试的方法包括使用全套测试模式来执行第一组芯片的基线测试，以及对于被识别为故障的芯片，确定全集中每个测试模式的得分。 该分数表示测试图案相对于其他测试图案唯一地识别故障芯片的能力。 在基线测试之后，使用由基线测试确定的具有最高平均分数的测试模式的一组减少的集合来执行第二组芯片的简化测试。 在精简测试之后，使用完整的测试模式进行第三组芯片的全面测试，并更新每种模式的平均分数。 进一步的测试在简化的测试和对另外一组芯片的完整测试之间进行了交替。

    Method of adding fabrication monitors to integrated circuit chips
    3.
    发明授权
    Method of adding fabrication monitors to integrated circuit chips 失效
    将制造监控器添加到集成电路芯片的方法

    公开(公告)号：US07620931B2

    公开(公告)日：2009-11-17

    申请号：US11859890

    申请日：2007-09-24

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    IPC分类号： G06F17/50

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

    摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

    Method for monitoring thermal control
    5.
    发明授权
    Method for monitoring thermal control 有权
    监控热控制的方法

    公开(公告)号：US08087823B2

    公开(公告)日：2012-01-03

    申请号：US12193497

    申请日：2008-08-18

    申请人： Francois Aube ,  Timothy M. Curtin ,  Matthew S. Grady ,  Thomas P. Scanlon ,  Eric N. Smith

    发明人： Francois Aube ,  Timothy M. Curtin ,  Matthew S. Grady ,  Thomas P. Scanlon ,  Eric N. Smith

    IPC分类号： G01K1/00 ,  G01K7/00 ,  G01K3/00 ,  H01L35/00

    CPC分类号： G01K7/01 ,  G01K15/00 ,  G01R31/2874

    摘要： A structure has a heat dissipating feature, an internal temperature measurement device, and a memory. The structure generates heat as power is supplied to the structure, and a threshold voltage of the internal temperature measurement device changes as the temperature of the temperature measurement device changes. The embodiments herein establish a linear relationship between temperature and threshold voltage by heating the structure to a first temperature and recording a first threshold voltage, and then heating the structure to a second temperature and recording a second threshold voltage. From this, the embodiments herein calculate a linear relationship between temperature and threshold voltage. Further, the embodiments herein can calculate the temperatures of the structure based only upon the linear relationship and threshold voltages measured from internal temperature measurement device.

    摘要翻译： 结构具有散热特征，内部温度测量装置和存储器。 该结构在向结构供电时产生热量，并且内部温度测量装置的阈值电压随温度测量装置的温度变化而变化。 本文的实施例通过将结构加热到第一温度并记录第一阈值电压，然后将结构加热到第二温度并记录第二阈值电压来建立温度和阈值电压之间的线性关系。 由此，这里的实施例计算温度和阈值电压之间的线性关系。 此外，这里的实施例可以仅基于从内部温度测量装置测量的线性关系和阈值电压来计算结构的温度。

    Method of adding fabrication monitors to integrated circuit chips
    7.
    发明授权
    Method of adding fabrication monitors to integrated circuit chips 有权
    将制造监控器添加到集成电路芯片的方法

    公开(公告)号：US07323278B2

    公开(公告)日：2008-01-29

    申请号：US11687731

    申请日：2007-03-19

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    IPC分类号： G03F9/00 ,  G03C5/00

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

    摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

    Designing scan chains with specific parameter sensitivities to identify process defects
    8.
    发明授权
    Designing scan chains with specific parameter sensitivities to identify process defects 失效
    设计具有特定参数灵敏度的扫描链，以识别过程缺陷

    公开(公告)号：US07194706B2

    公开(公告)日：2007-03-20

    申请号：US10710642

    申请日：2004-07-27

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

    摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。