公开(公告)号：US06926188B2

公开(公告)日：2005-08-09

申请号：US10700438

申请日：2003-11-04

申请人： Ichiro Hazeyama ,  Sakae Kitajo ,  Yuzo Shimada ,  Akeo Katahira ,  Jun Ishida ,  Masaru Terashima ,  Kazuhiko Futakami

发明人： Ichiro Hazeyama ,  Sakae Kitajo ,  Yuzo Shimada ,  Akeo Katahira ,  Jun Ishida ,  Masaru Terashima ,  Kazuhiko Futakami

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L21/683 ,  H05K3/34 ,  B23K1/00 ,  B23K5/00 ,  B23K20/14 ,  B23K35/12

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L21/6838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H05K3/3478 ,  H01L2924/00 ,  H01L2224/05599

摘要： Conductive balls are transferred from a pallet onto an array of conductive pads on a semiconductor chip by means of a transfer apparatus; the transfer apparatus includes a pallet formed with an array of recesses same in pattern as the array of conductive pads, a movable head formed with an array of vacuum holes and a driving mechanism for moving the head from an idle position onto the pallet and from the pallet to the semiconductor chip; when the head is moved to the pallet, the vacuum holes are connected to the recesses so as to confine the conductive balls in the narrow spaces; the vacuum is developed; then the conductive balls are traveled through the closed spaces to the vacuum holes; even if the conductive balls have been charged, the conductive balls are never attracted to the adjacent balls, and are surely captured by the vacuum holes.

摘要翻译： 导电球通过传送装置从托盘传送到半导体芯片上的导电焊盘阵列上; 转印装置包括形成有与导电垫阵列相同的凹槽阵列的托盘，形成有真空孔阵列的可移动头和用于将头从空闲位置移动到托盘上的驱动机构 托盘到半导体芯片; 当头部移动到托盘上时，真空孔连接到凹部，以将导电球限制在狭窄的空间中; 真空开发; 然后导电球通过封闭空间行进到真空孔; 即使导电球已经被充电，导电球也不会被吸引到相邻的球，并且被真空孔确实地捕获。

公开(公告)号：US07797519B2

公开(公告)日：2010-09-14

申请号：US12133032

申请日：2008-06-04

申请人： Masaru Terashima

发明人： Masaru Terashima

IPC分类号： G06F9/30

CPC分类号： G06F9/30058 ,  G06F9/30021 ,  G06F9/30094

摘要： There is disclosed a processing apparatus including, as an instruction set, a complex conditional branch instruction, and a condition setting instruction. The complex conditional branch instruction is an instruction for performing comparison operation for one or each of a plural number of conditions, and for performing branching to a branch target specified, based on comparison operation between the results of the comparison operations performed and the branching condition value specified. The condition setting instruction is an instruction for setting the condition. The processing apparatus includes a complex condition setting storage unit for storing the complex condition specified by the condition setting instruction, a condition comparison unit including a plurality of comparators for comparing the complex condition specified by the complex conditional branch instruction, in the complex condition setting storage unit, at the time of execution of the complex conditional branch instruction, a complex condition branching decision unit for determining on whether or not branching to the branch target is to be performed, using the results of comparisons performed in the comparators of the condition comparison unit and the branching condition value specified by the complex conditional branch instruction.

摘要翻译： 公开了一种处理装置，其包括作为指令集的复杂条件转移指令和条件设置指令。 复合条件转移指令是用于对多个条件中的一个或多个条件执行比较操作的指令，并且用于基于所执行的比较操作的结果和分支条件值之间的比较操作来执行对所指定的分支目标的分支 指定。 条件设置指令是用于设置条件的指令。 该处理装置包括：复合条件设置存储单元，用于存储由条件设置指令指定的复合条件;条件比较单元，包括多个比较器，用于将由复数条件转移指令指定的复数条件进行比较， 单元，在执行复杂条件分支指令时，使用在条件比较单元的比较器中执行的比较结果来确定是否执行对分支目标的分支的复合条件分支决定单元 以及由复数条件分支指令指定的分支条件值。

公开(公告)号：US20070234019A1

公开(公告)日：2007-10-04

申请号：US11723623

申请日：2007-03-21

申请人： Masaru Terashima

发明人： Masaru Terashima

IPC分类号： G06F9/44

CPC分类号： G06F9/30061 ,  G06F9/30094

摘要： Disclosed is a processor apparatus that has an instruction set that includes a complex conditional branch instruction that performs comparison operations corresponding to one or more conditions and causes a branch to a specified branch destination to be taken, based on a comparison operation between a result of the comparison operations and a specified branch condition value; and a condition setting instruction that sets a condition. The apparatus includes a plurality of condition setting/comparison units each of which is selected by an execution of the condition setting instruction, in each of which a condition specified by the condition setting instruction is set and, when the complex conditional branch instruction is executed, each of which performs a comparison operation corresponding to the condition specified by the condition setting instruction; and a complex conditional branch determination unit that determines whether to cause the branch to the branch destination to be taken or not, based on a result of a comparison between a result of the comparison operations of the plurality of condition setting/comparison units and the branch condition value specified by the complex conditional branch instruction.

摘要翻译： 公开了一种具有指令集的处理器装置，该指令集包括：复数条件转移指令，其执行与一个或多个条件相对应的比较操作，并且根据所述第 比较操作和指定的分支条件值; 以及设定条件的条件设定指示。 该设备包括多个条件设置/比较单元，每个条件设置/比较单元通过条件设置指令的执行来选择，每个条件设置/比较单元设置由条件设置指令指定的条件，并且当执行复数条件分支指令时， 每个执行与由条件设置指令指定的条件相对应的比较操作; 以及复数条件分支确定单元，其基于多个条件设置/比较单元的比较操作的结果与分支的比较结果，确定是否使分支到分支目的地被采用 由条件分支指令指定的条件值。

公开(公告)号：US06889886B2

公开(公告)日：2005-05-10

申请号：US10105580

申请日：2002-03-25

申请人： Ichiro Hazeyama ,  Sakae Kitajo ,  Yuzo Shimada ,  Akeo Katahira ,  Jun Ishida ,  Masaru Terashima ,  Kazuhiko Futakami

发明人： Ichiro Hazeyama ,  Sakae Kitajo ,  Yuzo Shimada ,  Akeo Katahira ,  Jun Ishida ,  Masaru Terashima ,  Kazuhiko Futakami

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L21/683 ,  H05K3/34 ,  B23K37/06 ,  B23K20/14 ,  B23K35/12

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L21/6838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H05K3/3478 ,  H01L2924/00 ,  H01L2224/05599

摘要： Conductive balls are transferred from a pallet onto an array of conductive pads on a semiconductor chip by means of a transfer apparatus; the transfer apparatus includes a pallet formed with an array of recesses same in pattern as the array of conductive pads, a movable head formed with an array of vacuum holes and a driving mechanism for moving the head from an idle position onto the pallet and from the pallet to the semiconductor chip; when the head is moved to the pallet, the vacuum holes are connected to the recesses so as to confine the conductive balls in the narrow spaces; the vacuum is developed; then the conductive balls are traveled through the closed spaces to the vacuum holes; even if the conductive balls have been charged, the conductive balls are never attracted to the adjacent balls, and are surely captured by the vacuum holes.

摘要翻译： 导电球通过传送装置从托盘传送到半导体芯片上的导电焊盘阵列上; 传送装置包括形成有与导电垫阵列相同的凹槽阵列的托盘，形成有真空孔阵列的可移动头和用于将头从空闲位置移动到托盘上的驱动机构 托盘到半导体芯片; 当头部移动到托盘上时，真空孔连接到凹部，以将导电球限制在狭窄的空间中; 真空开发; 然后导电球通过封闭空间行进到真空孔; 即使导电球已经被充电，导电球也不会被吸引到相邻的球，并且被真空孔确实地捕获。

公开(公告)号：US06538685B2

公开(公告)日：2003-03-25

申请号：US10004856

申请日：2001-12-07

申请人： Mikio Sugiyama ,  Masaru Terashima

发明人： Mikio Sugiyama ,  Masaru Terashima

IPC分类号： H04N714

CPC分类号： H04N7/152

摘要： A MCU unit of a video-meeting control system includes a volume level detector for detecting volume levels of a plurality of meeting terminals, a speaker terminal selection block for selecting a speaker terminal having a maximum volume level, mixing the voice data based on volume levels detected, and a mixer for mixing the voice data based on a specified mixing level of the speaker terminal, and transmitting the video data and the mixed voice data to the meeting terminals. The specified mixing level of the speaker terminal emphasizes the volume level of the speaker terminal.

公开(公告)号：US20090177874A1

公开(公告)日：2009-07-09

申请号：US12318726

申请日：2009-01-07

申请人： Masaru Terashima

发明人： Masaru Terashima

IPC分类号： G06F9/30

CPC分类号： G06F9/3806 ,  G06F9/30058 ,  G06F9/30094

摘要： Disclosed is a processor apparatus including a branch condition storage unit having a plurality of storage regions in each of which a branch condition set by a condition setting instruction is stored, an instruction decoder that decodes an instruction code, an instruction memory that stores therein the instruction code, an operation register used by a processor for operation, a branch condition comparison unit that performs a comparison operation for each of branch conditions, a conditional branch determination unit that makes a determination whether or not to perform program branching in a conditional branch instruction, a selector that makes selection between a branch destination address and a next instruction address, based on an output value of the condition branch determination unit, and a program counter that indicates a processor instruction executing position. The branch condition specified by the condition setting instruction is stored in one of the storage regions in the branch condition storage unit 1 specified by the condition setting instruction. When the conditional branch instruction is executed, individual determinations on a plurality of the branch conditions stored in the branch condition storage unit are made. Among the branch conditions that simultaneously hold, the branch address corresponding to the branch condition stored in a predetermined one of the storage regions in the branch condition storage unit is selected from the branch address storage unit, and branching to the branch address is performed.

摘要翻译： 公开了一种处理器装置，包括：分支条件存储单元，具有多个存储区域，每个存储区域存储有由条件设置指令设置的分支条件;指令解码器，对指令代码进行解码;指令存储器，其中存储指令 代码，用于操作的处理器使用的操作寄存器，执行每个分支条件的比较操作的分支条件比较单元，判定是否在条件分支指令中执行程序分支的条件分支确定单元， 选择器，其基于条件分支确定单元的输出值，以及指示处理器指令执行位置的程序计数器，在分支目的地地址和下一个指令地址之间进行选择。 由条件设置指令指定的分支条件存储在由条件设置指令指定的分支条件存储单元1中的一个存储区域中。 当执行条件分支指令时，对存储在分支条件存储单元中的多个分支条件进行单独的确定。 在同时保持的分支条件中，从分支地址存储单元中选择存储在分支条件存储单元中的预定的一个存储区域中的分支条件的分支地址，并且分支到分支地址。

公开(公告)号：US6043851A

公开(公告)日：2000-03-28

申请号：US6658

申请日：1998-01-13

申请人： Hideki Sawada ,  Takashi Sameshima ,  Masaru Terashima ,  Mitsumasa Tanaka

发明人： Hideki Sawada ,  Takashi Sameshima ,  Masaru Terashima ,  Mitsumasa Tanaka

IPC分类号： H04N5/92 ,  G11B27/10 ,  H04N5/04 ,  H04N5/60 ,  H04N5/93 ,  H04N7/52 ,  H04N19/00 ,  H04N19/102 ,  H04N19/132 ,  H04N19/196 ,  H04N19/423 ,  H04N19/44 ,  H04N19/503 ,  H04N19/577 ,  H04N19/587 ,  H04N19/70 ,  H04N19/85 ,  H04N9/475

CPC分类号： H04N21/4307 ,  H04N5/04 ,  H04N5/602 ,  H04N5/4401

摘要： An image and sound synchronizing reproduction apparatus includes a reference time calculation circuit for calculating a reference time in response to a data amount of decoded sound data, a delay detecting circuit calculating number of image frames to be processed practically in the decoding process in response to the reference time and comparing the number of image frames with number of frames practically processed in the decoding process, for detecting a delay of image decoding process, a frame-removing control circuit for performing a discriminating process of frames to be omitted the decoding process in response to the number of delay frames detected by the delay detecting circuit, and an image data input control circuit for performing an omission to read compressed image data corresponding to the frames discriminated by the frame-removing control circuit, controlling finely the image and sound synchronizing reproduction regardless of the structure of compressing coded data.

摘要翻译： 图像和声音同步再现装置包括：基准时间计算电路，用于响应于解码声音数据的数据量来计算基准时间;延迟检测电路，响应于所述解码处理实际上计算待处理的图像帧数; 参考时间，并且将图像帧的数量与在解码处理中实际处理的帧的数目进行比较，以检测图像解码处理的延迟;帧去除控制电路，用于响应于解码处理执行帧的识别处理 延迟检测电路检测的延迟帧的数量，以及图像数据输入控制电路，用于执行省略以读取与由帧除去控制电路鉴别的帧相对应的压缩图像数据，精细地控制图像和声音同步再现 而不管压缩编码数据的结构如何。

公开(公告)号：US20080313443A1

公开(公告)日：2008-12-18

申请号：US12133032

申请日：2008-06-04

申请人： Masaru TERASHIMA

发明人： Masaru TERASHIMA

IPC分类号： G06F9/32

CPC分类号： G06F9/30058 ,  G06F9/30021 ,  G06F9/30094

摘要： There is disclosed a processing apparatus including, as an instruction set, a complex conditional branch instruction, and a condition setting instruction. The complex conditional branch instruction is an instruction for performing comparison operation for one or each of a plural number of conditions, and for performing branching to a branch target specified, based on comparison operation between the results of the comparison operations performed and the branching condition value specified. The condition setting instruction is an instruction for setting the condition. The processing apparatus includes a complex condition setting storage unit for storing the complex condition specified by the condition setting instruction, a condition comparison unit including a plurality of comparators for comparing the complex condition specified by the complex conditional branch instruction, in the complex condition setting storage unit, at the time of execution of the complex conditional branch instruction, a complex condition branching decision unit for determining on whether or not branching to the branch target is to be performed, using the results of comparisons performed in the comparators of the condition comparison unit and the branching condition value specified by the complex conditional branch instruction.

摘要翻译： 公开了一种处理装置，其包括作为指令集的复杂条件转移指令和条件设置指令。 复合条件转移指令是用于对多个条件中的一个或多个条件执行比较操作的指令，并且用于基于所执行的比较操作的结果和分支条件值之间的比较操作来执行对所指定的分支目标的分支 指定。 条件设置指令是用于设置条件的指令。 该处理装置包括：复合条件设置存储单元，用于存储由条件设置指令指定的复合条件;条件比较单元，包括多个比较器，用于将由复数条件转移指令指定的复数条件进行比较， 单元，在执行复杂条件分支指令时，使用在条件比较单元的比较器中执行的比较结果来确定是否执行对分支目标的分支的复合条件分支决定单元 以及由复数条件分支指令指定的分支条件值。

公开(公告)号：US6163647A

公开(公告)日：2000-12-19

申请号：US982977

申请日：1997-12-02

申请人： Masaru Terashima ,  Takashi Samejima ,  Mitsumasa Tanaka ,  Hideki Sawada

发明人： Masaru Terashima ,  Takashi Samejima ,  Mitsumasa Tanaka ,  Hideki Sawada

IPC分类号： H04N5/92 ,  G11B20/10 ,  H04N5/93 ,  H04N9/804 ,  H04N9/806 ,  H04N19/00 ,  H04N19/102 ,  H04N19/132 ,  H04N19/146 ,  H04N19/196 ,  H04N19/423 ,  H04N19/587 ,  H04N19/70 ,  H04N5/928

CPC分类号： H04N21/4307 ,  H04N9/8042 ,  H04N9/8063 ,  H04N21/4341

摘要： An apparatus for producing synchronized playback of compressed digital data of audio-video signals from a desired portion of the digital data. The apparatus can be used in a system having comparatively low data processing ability, and work independent of the resolution of a software timer of the system. The apparatus comprises a frame counter for obtaining a reference time indicating reproduction time passage of the audio signal component from a reproduced data amount of the audio signal component. A delay detector detects progress of the video signal component in reference to the reference time.

摘要翻译： 一种用于从数字数据的期望部分产生音频 - 视频信号的压缩数字数据的同步重放的装置。 该装置可以用在具有相对低的数据处理能力的系统中，并且独立于系统的软件定时器的分辨率工作。 该装置包括帧计数器，用于从音频信号分量的再现数据量获得指示音频信号分量的再现时间通过的参考时间。 参考时间，延迟检测器检测视频信号分量的进展。

公开(公告)号：US6163646A

公开(公告)日：2000-12-19

申请号：US959196

申请日：1997-10-28

申请人： Mitsumasa Tanaka ,  Takashi Sameshima ,  Masaru Terashima ,  Hideki Sawada

发明人： Mitsumasa Tanaka ,  Takashi Sameshima ,  Masaru Terashima ,  Hideki Sawada

IPC分类号： H04N5/92 ,  H04N5/781 ,  H04N5/85 ,  H04N5/93 ,  H04N9/804 ,  H04N9/806 ,  H04N9/877 ,  H04N5/76

CPC分类号： H04N21/4307 ,  H04N5/781 ,  H04N5/85 ,  H04N9/8047 ,  H04N9/8063 ,  H04N9/877

摘要： To provide an apparatus for a synchronized playback of compressed digital data of audio-video signals with a simple configuration to be applied to a system having comparatively low data processing ability, independent of resolution of a software timer of the system, the apparatus of the invention obtains a reference time indicating reproduction time passage of the audio signal component from reproduced data amount of the audio signal component, and detects progress of the video signal component in reference to the reference time.

摘要翻译： 为了提供用于以简单的配置来同步回放音频 - 视频信号的压缩数字数据的装置，以适用于具有相对低的数据处理能力的系统，与系统的软件定时器的分辨率无关，本发明的装置 从音频信号分量的再现数据量获得指示音频信号分量的再现时间通过的参考时间，并且参考参考时间检测视频信号分量的进度。