公开(公告)号：US20150095627A1

公开(公告)日：2015-04-02

申请号：US14040016

申请日：2013-09-27

Applicant: Mark J. DECHENE ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Tong LI ,  Christine E. WANG

Inventor： Mark J. DECHENE ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Tong LI ,  Christine E. WANG

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F8/445 ,  G06F8/47 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/45508 ,  G06F9/461

Abstract: In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.

Abstract translation: 响应于检测到一个或多个条件被满足，可以创建线程的当前状态的检查点。 可以将一个或多个不完整的指令从重新排序缓冲器的第一级移动到重新排序缓冲器的第二级。 每个不完整的指令可能正在执行或等待执行。

公开(公告)号：US09652236B2

公开(公告)日：2017-05-16

申请号：US14139263

申请日：2013-12-23

Applicant: Srikanth T. Srinivasan ,  Mark J. Dechene ,  Yury N. Ilin ,  Justin M. Deinlein ,  Christine E. Wang ,  Matthew C. Merten

Inventor： Srikanth T. Srinivasan ,  Mark J. Dechene ,  Yury N. Ilin ,  Justin M. Deinlein ,  Christine E. Wang ,  Matthew C. Merten

IPC: G06F9/26 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3885

Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

公开(公告)号：US20140156977A1

公开(公告)日：2014-06-05

申请号：US13994699

申请日：2011-12-28

Applicant: Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

Inventor： Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3885

Abstract: Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.

Abstract translation: 描述了在微处理器中启用和/或禁用辅助跳转执行单元（JEU）的技术。 次级JEU被并入微处理器以与主JEU同时操作，并且能够在多个分支上处理同时的分支错误预测。 次级JEU的激活和停用可以由压力计数器或置信计数器来控制。 压力计数器机构增加在处理器内执行的每个分支操作的计数，并在每个周期期间将计数减去衰减值。 置信度计数机制增加每个正确预测分支的计数，并减少每个错误预测的计数。 当计数器超过激活阈值时，每个计数器发出一个激活组件，例如端口绑定硬件组件，开始将微操作绑定到辅助JEU。 计数器机制可能是线程不可知或线程特定的。

公开(公告)号：US20150178077A1

公开(公告)日：2015-06-25

申请号：US14139263

申请日：2013-12-23

Applicant: SRIKANTH T. SRINIVASAN ,  MARK J. DECHENE ,  YURY N. ILIN ,  JUSTIN M. DEINLEIN ,  CHRISTINE E. WANG ,  MATTHEW C. MERTEN

Inventor： SRIKANTH T. SRINIVASAN ,  MARK J. DECHENE ,  YURY N. ILIN ,  JUSTIN M. DEINLEIN ,  CHRISTINE E. WANG ,  MATTHEW C. MERTEN

IPC: G06F9/30

CPC classification number: G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3885

Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

Abstract translation: 处理器包括执行第一指令和第二指令的逻辑。 第一条指令在第二条指令之前被排序。 每个指令引用分配给相应物理寄存器的相应逻辑寄存器。 该处理器还包括在退出第一指令之前将第二指令的物理寄存器重新分配给另一个逻辑寄存器的逻辑。