公开(公告)号：US20150007188A1

公开(公告)日：2015-01-01

申请号：US13931864

申请日：2013-06-29

Applicant: Bambang SUTANTO ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Chia Yin Kevin LAI ,  Ammon J CHRISTIANSEN ,  Justin M DEINLEIN

Inventor： Bambang SUTANTO ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Chia Yin Kevin LAI ,  Ammon J CHRISTIANSEN ,  Justin M DEINLEIN

IPC: G06F9/50

CPC classification number: G06F9/384 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/4881

Abstract: A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one embodiment of the invention includes the operations of: classifying a plurality of operations based on the execution ports usable to execute those operations; allocating the plurality of operations into groups within a reservation station based on the classification, wherein each group is serviced by one or more execution ports corresponding to the classification, and wherein two or more entries within a group share a common read port and a common write port; dynamically scheduling two or more operations in a group for concurrent execution based on the ports capable of executing those operations and a relative age of the operations.

Abstract translation: 描述了用于在保留站内执行的调度操作的处理器和方法。 例如，根据本发明的一个实施例的方法包括以下操作：基于可用于执行这些操作的执行端口对多个操作进行分类; 基于分类，将多个操作分配到保留站内的组中，其中每个组由对应于分类的一个或多个执行端口服务，并且其中组内的两个或多个条目共享公共读取端口和公共写入 港口; 基于能够执行这些操作的端口和操作的相对年龄，动态地调度用于并发执行的组中的两个或更多个操作。

公开(公告)号：US20140181476A1

公开(公告)日：2014-06-26

申请号：US13723684

申请日：2012-12-21

Applicant: Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

Inventor： Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

IPC: G06F9/30

CPC classification number: G06F9/3838

Abstract: A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

Abstract translation: 公开了实现具有限制条目的依赖矩阵的调度器。 本公开的处理装置包括：解码单元，用于对指令进行解码;以及可通信地耦合到解码单元的调度器。 在一个实施例中，调度器被配置为接收解码的指令，确定解码的指令限定为由调度器维护的依赖矩阵中的受限保留站（RS）条目类型的分配，识别依赖矩阵中的RS条目 将所识别的空闲RS条目中的一个分配给依赖矩阵中的解码指令的信息，并且通过解码指令的源依赖性信息更新与所要求的RS条目相对应的依赖矩阵的一行。

公开(公告)号：US09652236B2

公开(公告)日：2017-05-16

申请号：US14139263

申请日：2013-12-23

Applicant: Srikanth T. Srinivasan ,  Mark J. Dechene ,  Yury N. Ilin ,  Justin M. Deinlein ,  Christine E. Wang ,  Matthew C. Merten

Inventor： Srikanth T. Srinivasan ,  Mark J. Dechene ,  Yury N. Ilin ,  Justin M. Deinlein ,  Christine E. Wang ,  Matthew C. Merten

IPC: G06F9/26 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3885

Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

公开(公告)号：US20150178077A1

公开(公告)日：2015-06-25

申请号：US14139263

申请日：2013-12-23

Applicant: SRIKANTH T. SRINIVASAN ,  MARK J. DECHENE ,  YURY N. ILIN ,  JUSTIN M. DEINLEIN ,  CHRISTINE E. WANG ,  MATTHEW C. MERTEN

Inventor： SRIKANTH T. SRINIVASAN ,  MARK J. DECHENE ,  YURY N. ILIN ,  JUSTIN M. DEINLEIN ,  CHRISTINE E. WANG ,  MATTHEW C. MERTEN

IPC: G06F9/30

CPC classification number: G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3885

Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

Abstract translation: 处理器包括执行第一指令和第二指令的逻辑。 第一条指令在第二条指令之前被排序。 每个指令引用分配给相应物理寄存器的相应逻辑寄存器。 该处理器还包括在退出第一指令之前将第二指令的物理寄存器重新分配给另一个逻辑寄存器的逻辑。

公开(公告)号：US20140189306A1

公开(公告)日：2014-07-03

申请号：US13728273

申请日：2012-12-27

Applicant: Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

Inventor： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

Abstract: An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

Abstract translation: 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

公开(公告)号：US10235180B2

公开(公告)日：2019-03-19

申请号：US13723684

申请日：2012-12-21

Applicant: Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

Inventor： Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

IPC: G06F9/30 ,  G06F9/38

Abstract: A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

公开(公告)号：US09354875B2

公开(公告)日：2016-05-31

申请号：US13728273

申请日：2012-12-27

Applicant: Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

Inventor： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

Abstract: An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

Abstract translation: 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。