公开(公告)号：USD281355S

公开(公告)日：1985-11-12

申请号：US538723

申请日：1983-10-03

Applicant: Lawrence R. Fraley ,  Arnold E. Westlund, Jr.

Designer： Lawrence R. Fraley ,  Arnold E. Westlund, Jr.

公开(公告)号：US07161810B2

公开(公告)日：2007-01-09

申请号：US11238960

申请日：2005-09-30

Applicant: Lawrence R. Fraley ,  Voya Markovich

Inventor： Lawrence R. Fraley ,  Voya Markovich

IPC: H05K7/06 ,  H05K7/20 ,  H01L23/34

CPC classification number: H01L23/145 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

Abstract translation: 一种多芯片电子封装，其利用位于载体的上表面上的堆叠取向的有机层压芯片载体和一对半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片中的一个或两个耦合到其底表面上的下面的导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。 第一芯片（例如ASIC芯片）被焊接到载体上，而第二芯片（例如存储器芯片）被固定到第一芯片的上表面并且使用多个引线键合连接到载体。

公开(公告)号：US07023707B2

公开(公告)日：2006-04-04

申请号：US10394135

申请日：2003-03-24

Applicant: Lawrence R. Fraley ,  Voya R. Markovich

Inventor： Lawrence R. Fraley ,  Voya R. Markovich

IPC: H05K7/06 ,  H05K7/20 ,  H01L23/34 ,  H01L23/58

CPC classification number: H01L23/5383 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  H01L2224/0401

Abstract: An information handling system, e.g., computer, server or mainframe, which includes a multi-chip electronic package utilizing an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities of the final system product.

Abstract translation: 信息处理系统，例如计算机，服务器或主机，其包括利用有机层压芯片载体的多芯片电子封装以及位于载体的上表面上的多个半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片连接到其底表面上的底层导体。 载体可以包括高速部分以确保半导体芯片之间的高频连接，并且还可以包括用于增强最终系统产品的操作能力的内部电容器和/或导热构件。

公开(公告)号：US4229161A

公开(公告)日：1980-10-21

申请号：US33

申请日：1979-01-02

Applicant: Andre C. Bouchard ,  Lawrence R. Fraley

Inventor： Andre C. Bouchard ,  Lawrence R. Fraley

IPC: F21K5/08 ,  F21K5/02

CPC classification number: F21K5/02

Abstract: An electrically-activated photoflash lamp which includes a thin member (e.g. a mica disk) therein located between the lamp's combustible shreds and primer material. The disk prevents the shreds from contacting the primer material and any portions of the lamp's electrical conductors which have access to the interior of the envelope. A method of making the lamp is also provided.

Abstract translation: 一种电激活的闪光灯，其包括位于灯的可燃碎片和底漆材料之间的薄构件（例如云母盘）。 盘片防止碎片与底漆材料和灯泡电导体的任何可以进入信封内部的部分接触。 还提供了制造灯的方法。

公开(公告)号：US06992896B2

公开(公告)日：2006-01-31

申请号：US10661616

申请日：2003-09-15

Applicant: Lawrence R. Fraley ,  Voya Markovich

Inventor： Lawrence R. Fraley ,  Voya Markovich

IPC: H05K7/06 ,  H05K7/20 ,  H01L23/34

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H01L2224/0401

Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

公开(公告)号：US4545000A

公开(公告)日：1985-10-01

申请号：US715584

申请日：1985-03-25

Applicant: Lawrence R. Fraley ,  Arnold E. Westlund, Jr.

Inventor： Lawrence R. Fraley ,  Arnold E. Westlund, Jr.

IPC: F21V7/09 ,  F21V7/00

CPC classification number: F21V7/09

Abstract: An improved projection lamp unit including a glass reflector having a concave reflecting surface and a tungsten halogen lamp positioned within the concavity of the reflector. The concave reflecting surface of the reflector is provided with alternately disposed radially extending regions including a series of specular stripes in combination with alternately spaced regions of facets. Preferably four or five stripes and an associated four or five facet regions are provided.

Abstract translation: 一种改进的投影灯单元，其包括具有凹面反射面的玻璃反射体和位于反射体的凹部内的卤素灯。 反射器的凹面反射表面设置有交替设置的径向延伸的区域，其包括一系列镜面条纹以及交替间隔的小平面区域的组合。 优选地提供四个或五个条纹和相关联的四个或五个面区域。

公开(公告)号：US4161388A

公开(公告)日：1979-07-17

申请号：US778395

申请日：1977-03-17

Applicant: Andre C. Bouchard ,  Lawrence R. Fraley

Inventor： Andre C. Bouchard ,  Lawrence R. Fraley

IPC: F21V9/16 ,  G03B15/04 ,  F21K5/02 ,  F21K2/00 ,  F21L25/00

CPC classification number: F21V9/16 ,  F21L11/00

Abstract: A flashlamp signal device which includes an illumination means for providing a prolonged, visible signal after actuation of each of the device's flashlamps. The illumination means may be in the form of a phosphor coating within the device or on an adjacent, movable panel, or the phosphor may be impregnated within the light-transmitting housing or support structure of the device.

Abstract translation: 一种闪光灯信号装置，其包括照明装置，用于在致动每个装置的闪光灯之后提供延长的可见信号。 照明装置可以是在装置内或相邻的可移动面板上的荧光体涂层的形式，或者磷光体可以浸渍在装置的透光壳体或支撑结构内。

公开(公告)号：US07665207B2

公开(公告)日：2010-02-23

申请号：US11455183

申请日：2006-06-19

Applicant: Lawrence R. Fraley ,  Voya Markovich

Inventor： Lawrence R. Fraley ,  Voya Markovich

IPC: H05K3/30

CPC classification number: H01L23/145 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

Abstract translation: 一种制造多芯片电子封装的方法，该多芯片电子封装利用有机层压芯片载体和位于载体的上表面上的堆叠取向的一对半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片中的一个或两个耦合到其底表面上的下面的导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。 第一芯片（例如ASIC芯片）被焊接到载体上，而第二芯片（例如存储器芯片）被固定到第一芯片的上表面并且使用多个引线键合连接到载体。

公开(公告)号：US07035113B2

公开(公告)日：2006-04-25

申请号：US10394107

申请日：2003-03-24

Applicant: Lawrence R. Fraley ,  Voya R. Markovich

Inventor： Lawrence R. Fraley ,  Voya R. Markovich

IPC: H05K7/06 ,  H05K7/20 ,  H01L23/34 ,  H01L23/58

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H01L2224/0401

Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.

Abstract translation: 一种多芯片电子封装，其利用位于载体的上表面上的有机层压芯片载体和多个半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片连接到其底表面上的底层导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。