公开(公告)号：US08418091B2

公开(公告)日：2013-04-09

申请号：US12578441

申请日：2009-10-13

Applicant: Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald P. Cocchi

Inventor： Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald P. Cocchi

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5045 ,  G06F21/75 ,  H01L27/0203 ,  H01L27/0207

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.

Abstract translation: 一种用于伪装专用集成电路（ASIC）的方法和装置，其中所述ASIC包括多个互连的功能逻辑。 该方法将功能上的惰性元件添加到逻辑描述中，或提供标准逻辑单元的替代定义，使得难以使用逆向工程程序来发现电路的功能。

公开(公告)号：US08258583B1

公开(公告)日：2012-09-04

申请号：US12949657

申请日：2010-11-18

Applicant: Lap-Wai Chow ,  William M. Clark, Jr. ,  Gavin J. Harbison ,  James P. Baukus

Inventor： Lap-Wai Chow ,  William M. Clark, Jr. ,  Gavin J. Harbison ,  James P. Baukus

IPC: H01L27/088

CPC classification number: H01L27/0203 ,  G06K19/073 ,  G06K19/07363 ,  H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

Abstract translation: 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。

公开(公告)号：US20120139582A1

公开(公告)日：2012-06-07

申请号：US13370118

申请日：2012-02-09

Applicant: Ronald P. Cocchi ,  Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang

Inventor： Ronald P. Cocchi ,  Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang

IPC: H03K19/177 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F21/14 ,  H01L27/0207 ,  H01L27/11807 ,  H03K19/17736

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

Abstract translation: 一种用于伪装专用集成电路（ASIC）的方法和装置，其中所述ASIC包括多个互连的功能逻辑。 该方法将功能上的惰性元件添加到逻辑描述中，或提供标准逻辑单元的替代定义，使得难以使用逆向工程程序来发现电路的功能。 此外，可以在GDS层上执行后处理以提供空白空间的实际填充，以便类似于在功能电路中找到的结构元素。

公开(公告)号：US08151235B2

公开(公告)日：2012-04-03

申请号：US12380094

申请日：2009-02-24

Applicant: Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald P. Cocchi

Inventor： Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald P. Cocchi

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F21/14 ,  H01L27/0207

Abstract: A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells.

Abstract translation: 一种用于伪装专用集成电路（ASIC）的方法，装置，制品和存储器结构，其中ASIC包括多个互连的功能逻辑单元。 在一个实施例中，该方法包括以下步骤：识别在其中没有功能逻辑的多个互连功能逻辑单元之间的至少一个间隙，将一个填充单元或填充单元的组合放置在所识别的间隙中并限定放置的填充物 细胞。

公开(公告)号：US07935603B1

公开(公告)日：2011-05-03

申请号：US11807896

申请日：2007-05-29

Applicant: Lap-Wai Chow ,  William M. Clark, Jr. ,  Gavin J. Harbison ,  Paul Ou Yang

Inventor： Lap-Wai Chow ,  William M. Clark, Jr. ,  Gavin J. Harbison ,  Paul Ou Yang

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L23/573 ,  H01L27/0203 ,  Y10S257/90

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.

公开(公告)号：US07888213B2

公开(公告)日：2011-02-15

申请号：US11375846

申请日：2006-03-14

Applicant: Lap-Wai Chow ,  William M. Clark, Jr. ,  Gavin J. Harbison ,  James P. Baukus

Inventor： Lap-Wai Chow ,  William M. Clark, Jr. ,  Gavin J. Harbison ,  James P. Baukus

IPC: H01L21/8236

CPC classification number: H01L27/0203 ,  G06K19/073 ,  G06K19/07363 ,  H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

Abstract translation: 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。

公开(公告)号：US20100218158A1

公开(公告)日：2010-08-26

申请号：US12578441

申请日：2009-10-13

Applicant: Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald Ronald Cocchi

Inventor： Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald Ronald Cocchi

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5045 ,  G06F21/75 ,  H01L27/0203 ,  H01L27/0207

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.

Abstract translation: 一种用于伪装专用集成电路（ASIC）的方法和装置，其中所述ASIC包括多个互连的功能逻辑。 该方法将功能惰性元素添加到逻辑描述中，或提供标准逻辑单元的替代定义，以使得难以使用逆向工程程序来发现电路的功能。

公开(公告)号：US20100213974A1

公开(公告)日：2010-08-26

申请号：US12380094

申请日：2009-02-24

Applicant: Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald P. Cocchi

Inventor： Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang ,  Ronald P. Cocchi

IPC: H03K19/173 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F21/14 ,  H01L27/0207

Abstract: A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells.

Abstract translation: 一种用于伪装专用集成电路（ASIC）的方法，装置，制品和存储器结构，其中ASIC包括多个互连的功能逻辑单元。 在一个实施例中，该方法包括以下步骤：识别在其中没有功能逻辑的多个互连功能逻辑单元之间的至少一个间隙，将一个填充单元或填充单元的组合放置在所识别的间隙中并限定放置的填充物 细胞。

公开(公告)号：US07514755B2

公开(公告)日：2009-04-07

申请号：US10735841

申请日：2003-12-12

Applicant: Lap-Wai Chow ,  William M. Clark, Jr. ,  James P. Baukus ,  Gavin J. Harbison

Inventor： Lap-Wai Chow ,  William M. Clark, Jr. ,  James P. Baukus ,  Gavin J. Harbison

IPC: H01L29/76

CPC classification number: H01L21/823892 ,  H01L27/02

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

Abstract translation: 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。

公开(公告)号：US07008873B2

公开(公告)日：2006-03-07

申请号：US11089415

申请日：2005-03-23

Applicant: Lap-Wai Chow ,  William M. Clark, Jr. ,  James P. Baukus

Inventor： Lap-Wai Chow ,  William M. Clark, Jr. ,  James P. Baukus

IPC: H01L21/44 ,  H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/4763

CPC classification number: H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.