知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.021 seconds)

    Methods for Minimizing Edge Peeling in the Manufacturing of BSI Chips
    1.
    发明申请
    Methods for Minimizing Edge Peeling in the Manufacturing of BSI Chips 有权
    在BSI芯片制造中最小化边缘剥离的方法

    公开(公告)号：US20140024170A1

    公开(公告)日：2014-01-23

    申请号：US13551457

    申请日：2012-07-17

    Applicant: Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    Inventor： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    IPC: H01L31/18

    CPC classification number: H01L27/1464 ,  H01L21/02087 ,  H01L21/0209 ,  H01L27/14687

    Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.

    Abstract translation: 一种方法包括在半导体衬底上形成顶部金属线，其中半导体衬底是具有斜面的晶片的一部分。 当顶部金属线暴露时，在斜面上提供蚀刻剂，其中用蚀刻剂喷射的晶片的区域具有形成具有第一直径的第一环的内部限定线。 进行修整步骤以修剪晶片的边缘部分，其中晶片的剩余部分的边缘具有基本上等于或小于第一直径的第二直径。

    Apparatus for Wafer Grinding
    2.
    发明申请
    Apparatus for Wafer Grinding 有权

    公开(公告)号：US20130023188A1

    公开(公告)日：2013-01-24

    申请号：US13188028

    申请日：2011-07-21

    Applicant: Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Chun-Ting Kuo

    Inventor： Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Chun-Ting Kuo

    IPC: B24B1/00 ,  B24B7/00

    CPC classification number: B24B7/228 ,  B24D7/14

    Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.

    Feature dimension measurement
    3.
    发明授权
    Feature dimension measurement 有权
    特征尺寸测量

    公开(公告)号：US08049213B2

    公开(公告)日：2011-11-01

    申请号：US11958942

    申请日：2007-12-18

    Applicant: Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    Inventor： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    IPC: H01L21/66 ,  H01L23/544

    CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/20

    Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.

    Abstract translation: 测量尺寸特性的方法包括提供衬底并在衬底上形成反射层。 然后在反射层上形成电介质层。 电介质层包括在透明区域内插入的光栅图案和电阻率测试线。 然后将辐射引导到电介质层上，使得一些辐射透过透明区域到达反射层。 然后从由金属光栅图案反射和散射的辐射中检测出辐射图。 分析辐射图以确定第一维信息。 然后测量电阻率测试线的电阻，并分析该电阻以确定第二维信息。 然后比较第一和第二维信息。

    Feature Dimension Measurement
    4.
    发明申请
    Feature Dimension Measurement 有权
    特征尺寸测量

    公开(公告)号：US20090152545A1

    公开(公告)日：2009-06-18

    申请号：US11958942

    申请日：2007-12-18

    Applicant: Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    Inventor： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    IPC: H01L23/58 ,  H01L21/66

    CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/20

    Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.

    Abstract translation: 测量尺寸特性的方法包括提供衬底并在衬底上形成反射层。 然后在反射层上形成电介质层。 电介质层包括在透明区域内插入的光栅图案和电阻率测试线。 然后将辐射引导到电介质层上，使得一些辐射透过透明区域到达反射层。 然后从由金属光栅图案反射和散射的辐射中检测出辐射图。 分析辐射图以确定第一维信息。 然后测量电阻率测试线的电阻，并分析该电阻以确定第二维信息。 然后比较第一和第二维信息。

    Removal of SiON residue after CMP
    5.
    发明授权
    Removal of SiON residue after CMP 失效
    CMP后去除SiON残留物

    公开(公告)号：US06828226B1

    公开(公告)日：2004-12-07

    申请号：US10042573

    申请日：2002-01-09

    Applicant: Kei-Wei Chen ,  Kuo-Hsiu Wei ,  Yu-Kin Lin ,  Ting-Chun Wang ,  Ying-Lang Wang ,  Shih-Tzung Chang

    Inventor： Kei-Wei Chen ,  Kuo-Hsiu Wei ,  Yu-Kin Lin ,  Ting-Chun Wang ,  Ying-Lang Wang ,  Shih-Tzung Chang

    IPC: H01L214763

    CPC classification number: H01L21/3212 ,  H01L21/02052 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/7684

    Abstract: For 0.18 micron technology, it is common practice to use silicon oxynitride as an anti-reflective layer for defining the via etch patterns. It has however been found that, using current technology, residual particles of oxynitride get left behind. The present invention solves this problem by subjecting the surface from which the silicon oxynitride was removed to a high pressure rinse of an aqueous solution that includes a surfactant such as tetramethyl ammonium hydroxide or isopropyl alcohol. These surfactants serve to modify the hydrophobic behavior of the silicon oxynitride particles so that they no longer cling to the surface.

    Abstract translation: 对于0.18微米技术，通常的做法是使用氮氧化硅作为抗反射层来定义通孔蚀刻图案。 然而，已经发现，使用当前的技术，留下残留的氮氧化物颗粒。 本发明通过将去除了氮氧化硅的表面经受包括诸如四甲基氢氧化铵或异丙醇的表面活性剂的水溶液的高压冲洗来解决这个问题。 这些表面活性剂用于改变氮氧化硅颗粒的疏水性能，使得它们不再粘附到表面。

    MODULAR GRINDING APPARATUSES AND METHODS FOR WAFER THINNING
    7.
    发明申请
    MODULAR GRINDING APPARATUSES AND METHODS FOR WAFER THINNING 有权
    模块化研磨设备及其减薄方法

    公开(公告)号：US20130210321A1

    公开(公告)日：2013-08-15

    申请号：US13370946

    申请日：2012-02-10

    Applicant: Chun-Ting KUO ,  Kei-Wei CHEN ,  Ying-Lang WANG ,  Kuo-Hsiu WEI

    Inventor： Chun-Ting KUO ,  Kei-Wei CHEN ,  Ying-Lang WANG ,  Kuo-Hsiu WEI

    IPC: H01L21/02 ,  B24B7/00

    CPC classification number: H01L21/304 ,  B24B37/00 ,  B24B37/042

    Abstract: Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.

    Abstract translation: 公开了使多个半导体晶片变薄的方法及其实施方法。 一组研磨模块内的研磨模块接收并研磨半导体晶片。 抛光模块从研磨模块接收半导体晶片并抛光晶片。 抛光模块被配置为在比研磨模块构造成磨碎相应晶片的时间少的时间内抛光半导体晶片。

    Modular grinding apparatuses and methods for wafer thinning
    10.
    发明授权
    Modular grinding apparatuses and methods for wafer thinning 有权
    用于晶片薄化的模块化研磨装置和方法

    公开(公告)号：US09570311B2

    公开(公告)日：2017-02-14

    申请号：US13370946

    申请日：2012-02-10

    Applicant: Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    Inventor： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    IPC: H01L21/304 ,  B24B37/04 ,  B24B37/00

    CPC classification number: H01L21/304 ,  B24B37/00 ,  B24B37/042

    Abstract: Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.

    Abstract translation: 公开了使多个半导体晶片变薄的方法及其实施方法。 一组研磨模块内的研磨模块接收并研磨半导体晶片。 抛光模块从研磨模块接收半导体晶片并抛光晶片。 抛光模块被配置为在比研磨模块构造成磨碎相应晶片的时间少的时间内抛光半导体晶片。

Patent Agency Ranking