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    ROW HAMMER REFRESH COMMAND
    1.
    发明申请
    ROW HAMMER REFRESH COMMAND 有权

    公开(公告)号：US20140059287A1

    公开(公告)日：2014-02-27

    申请号：US14068677

    申请日：2013-10-31

    申请人： Kuljit BAINS ,  Johm HALBERT ,  Christopher MOZAK ,  Theodore SCHOENBORN ,  Zvika GREENFIELD

    发明人： Kuljit BAINS ,  Johm HALBERT ,  Christopher MOZAK ,  Theodore SCHOENBORN ,  Zvika GREENFIELD

    IPC分类号： G11C11/406

    CPC分类号： G11C11/40615 ,  G11C7/02 ,  G11C11/40611 ,  G11C11/40622

    摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

    摘要翻译： 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中被重复访问时，物理上相邻的行（“受害者”行）可能经历数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

    Bus frequency adjustment circuitry for use in a dynamic random access memory device
    2.
    发明授权
    Bus frequency adjustment circuitry for use in a dynamic random access memory device 有权
    用于动态随机存取存储器件的总线频率调节电路

    公开(公告)号：US08458507B2

    公开(公告)日：2013-06-04

    申请号：US12163663

    申请日：2008-06-27

    申请人： Joe Salmon ,  Kuljit Bains

    发明人： Joe Salmon ,  Kuljit Bains

    IPC分类号： G06F1/04 ,  G06F1/10 ,  G06F13/16

    CPC分类号： G06F1/10 ,  G06F1/06

    摘要： A clock divider circuitry and method for use in a dynamic random access memory device. The method may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving the clock input signal and the output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving the multiplexed output at a first bus configured to receive the multiplexed output and to reduce an operational frequency of the first bus in response to an increase in an operational frequency of a second bus associated with the memory device.

    摘要翻译： 一种用于动态随机存取存储器件的时钟分频器电路和方法。 该方法可以包括：在时钟分频器电路处从时钟输入接收器接收具有第一频率的时钟输入信号，时钟分频器电路包括配置成产生输出信号的触发器，该触发器至少部分地基于反相输出信号 和时钟输入信号。 输出信号可以具有第二频率，其是第一频率的一部分。 该方法还可以包括在多路复用器处接收时钟输入信号和输出信号，并产生多路输出。 该方法可以另外包括：在被配置为接收多路复用输出的第一总线处接收多路复用输出并且响应于与存储器件相关联的第二总线的工作频率的增加而减小第一总线的工作频率。

    Memory device commands
    3.
    发明授权
    Memory device commands 有权
    内存设备命令

    公开(公告)号：US07454586B2

    公开(公告)日：2008-11-18

    申请号：US11093705

    申请日：2005-03-30

    申请人： Jun Shi ,  Sandeep Jain ,  Animesh Mishra ,  Kuljit Bains ,  David Wyatt ,  Thomas D. Skelton ,  Bill H. Nale

    发明人： Jun Shi ,  Sandeep Jain ,  Animesh Mishra ,  Kuljit Bains ,  David Wyatt ,  Thomas D. Skelton ,  Bill H. Nale

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G11C7/04 ,  G11C7/1045 ,  G11C11/4076

    摘要： Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.

    摘要翻译： 关于物理参数和安全性的数据以及发送这样的数据的命令可以使用连接在两者之间的存储器总线在存储器件和存储器控制器之间传送。 在一个实施例中，本发明包括在存储器总线上的存储器件处接收第一命令，第一命令不同于读取或写入命令，并且与第一命令一起接收第二命令，使用 第一个命令未使用的行。

    Memory transfer with early access to critical portion
    4.
    发明申请
    Memory transfer with early access to critical portion 有权
    具有早期访问关键部分的内存传输

    公开(公告)号：US20070244948A1

    公开(公告)日：2007-10-18

    申请号：US11392471

    申请日：2006-03-28

    申请人： Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

    发明人： Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

    IPC分类号： G06F7/78

    CPC分类号： G06F13/1678

    摘要： In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器 具有第二宽度的第二格式，其中临界部分包括在第一帧中。 关键部分可以包括在存储器设备等级上映射的高速缓存线。 描述和要求保护其他实施例。

    Method and apparatus for interfacing with heterogeneous dual in-line memory modules
    8.
    发明授权
    Method and apparatus for interfacing with heterogeneous dual in-line memory modules 有权
    用于与异构双列直插式存储器模块进行接口的方法和装置

    公开(公告)号：US08495330B2

    公开(公告)日：2013-07-23

    申请号：US12753355

    申请日：2010-04-02

    申请人： George Vergis ,  Kuljit Bains ,  Joe Salmon

    发明人： George Vergis ,  Kuljit Bains ,  Joe Salmon

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1694

    摘要： Described herein is a method and apparatus to interface a processor with a heterogeneous dual in-line memory module (DIMM). The method comprises determining an identity of a DIMM having data lanes; mapping the data lanes based on the determining of the identity of the DIMM; training input-output (I/O) transceivers in response to the mapping of the data lanes; and transferring data to and from the DIMM after training the I/O transceivers.

    摘要翻译： 这里描述的是将处理器与异构双列直插存储器模块（DIMM）进行接口的方法和装置。 该方法包括确定具有数据通道的DIMM的身份; 基于确定DIMM的身份来映射数据通道; 训练输入输出（I / O）收发器以响应数据通道的映射; 并在训练I / O收发器之后向DIMM传输数据。

    Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode
    10.
    发明申请
    Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode 失效
    使用相同存储器类型来支持错误检查模式和非错误检查模式的系统，方法和装置

    公开(公告)号：US20070220401A1

    公开(公告)日：2007-09-20

    申请号：US11364107

    申请日：2006-02-27

    申请人： Kuljit Bains

    发明人： Kuljit Bains

    IPC分类号： G11C29/00

    CPC分类号： G11C7/1045 ,  G06F11/1044 ,  G11C7/1006 ,  G11C29/42 ,  G11C29/52 ,  G11C2207/104

    摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type in an error check mode and a non-error check mode. In some embodiments, a memory device includes at least one split bank pair of memory banks. If the memory device is in an error check mode, then, in some embodiments, data is stored in one of memory banks of the split bank pair and the corresponding error check bits are stored in the other memory bank of the split bank pair. A register bit on the memory device indicates whether it is in the error check mode or the non-error check mode. Other embodiments are described and claimed.

    摘要翻译： 本发明的实施例一般涉及在错误检查模式和非错误检查模式中使用相同存储器类型的系统，方法和装置。 在一些实施例中，存储器设备包括至少一个分离组对的存储体。 如果存储器件处于错误检查模式，则在一些实施例中，数据被存储在分离组对的存储体之一中，并且相应的错误校验位存储在分离存储体对的另一个存储体中。 存储设备上的寄存器位指示是处于错误检查模式还是非错误检查模式。 描述和要求保护其他实施例。