公开(公告)号：US09548673B1

公开(公告)日：2017-01-17

申请号：US14948409

申请日：2015-11-23

Applicant: Ying-Zong Juang ,  Hann-Huei Tsai ,  Po-Chang Wu ,  Kuei-Cheng Lin ,  Chih-Yuan Yeh

Inventor： Ying-Zong Juang ,  Hann-Huei Tsai ,  Po-Chang Wu ,  Kuei-Cheng Lin ,  Chih-Yuan Yeh

IPC: H02M7/04

CPC classification number: H02M7/04 ,  H02M7/103 ,  H02M7/217

Abstract: The invention includes two parallel paths. A first path is composed of two contact ends of a first electronic switch and a first, third and fifth diodes, which connect in series. One contact end connects a first end of an AC source, and a control end connects a second end of the AC source. A second path is composed of two contact ends of a second electronic switch and a second, fourth and sixth diodes, which connect in series. One contact end connects the second end of the AC source, and a control end connects the first end of the AC source. The AC source is connected between the positive ends of the first and second diodes. The second end of the AC source separately connects negative ends of the first and third diodes through two capacitors. The first end of the AC source separately connects negative ends of the second and fourth diodes through another two capacitors. Negative ends of the fifth and sixth diodes connect together to form a voltage output end.

Abstract translation: 本发明包括两条平行路径。 第一路径由第一电子开关和串联连接的第一，第三和第五二极管的两个接触端组成。 一个接触端连接AC电源的第一端，控制端连接AC电源的第二端。 第二路径由第二电子开关和串联连接的第二，第四和第六二极管的两个接触端组成。 一个接触端连接AC电源的第二端，控制端连接AC电源的第一端。 AC源连接在第一和第二二极管的正极之间。 交流电源的第二端通过两个电容器将第一和第三二极管的负极分开连接。 交流电源的第一端通过另外两个电容器将第二和第四二极管的负极分开连接。 第五和第六二极管的负端连接在一起形成电压输出端。

公开(公告)号：US20130147560A1

公开(公告)日：2013-06-13

申请号：US13408414

申请日：2012-02-29

Applicant: Wei-Hsien CHEN ,  Kuei-Cheng Lin ,  Bing-Song Chen ,  Chien-Chih Lin

Inventor： Wei-Hsien CHEN ,  Kuei-Cheng Lin ,  Bing-Song Chen ,  Chien-Chih Lin

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F1/26 ,  H03F2203/45514 ,  H03F2203/45518 ,  H03F2203/45521 ,  H03F2203/45544

Abstract: A low noise amplifier with back-to-back connected diodes and a back-to-back connected diode with high impedance thereof are provided. The low noise amplifier includes a first operational amplifier (OP) and at least two first back-to-back connected diodes. The back-to-back connected diode with high impedance is formed from at least one MOS FET operated within a cut-off region. The first back-to-back connected diodes are connected electrically between the first input end and the first output end, and between the second input end and the second output end, of the first OP respectively. By the implementation of the present invention, the low noise amplifier is not only low noise, but also with low energy consumption, high stability, low circuitry complexity, and easily controlled manufacturing process.

Abstract translation: 提供了具有背对背连接的二极管和具有高阻抗的背对背连接二极管的低噪声放大器。 低噪声放大器包括第一运算放大器（OP）和至少两个第一背对背连接的二极管。 具有高阻抗的背对背连接的二极管由在截止区域内操作的至少一个MOS FET形成。 第一背对背连接的二极管分别在第一输入端和第一输出端之间以及第二输入端和第二输出端之间电连接。 通过实施本发明，低噪声放大器不仅具有低噪声，而且具有低能耗，高稳定性，低电路复杂性和容易控制的制造工艺。

公开(公告)号：US06323868B1

公开(公告)日：2001-11-27

申请号：US09238233

申请日：1999-01-27

Applicant: Edward John Paluch, Jr. ,  Kuei-Cheng Lin

Inventor： Edward John Paluch, Jr. ,  Kuei-Cheng Lin

IPC: G06F1206

CPC classification number: G06F13/4022

Abstract: The present invention comprises an efficient system and method for reading and writing data from memory that is organized to represent either field or frame video data in a wide-word configured memory. A memory controller is configured to read or write either sequential wide-words or alternate wide-words in a DMA transfer as directed by software. After the DMA transfer is initiated, the memory read or write operations proceed automatically until the DMA transfer is completed. The ability to read or write either sequential or alternate wide-words beneficially supports operations to convert between field video data for interlaced video displays and frame video data for progressive-scan displays.

Abstract translation: 本发明包括一种用于从存储器中读取和写入数据的有效系统和方法，其被组织为在宽字配置的存储器中表示字段或帧视频数据。 存储器控制器被配置为按照软件的指示在DMA传输中读取或写入顺序宽字或备用宽字。 DMA传输启动后，存储器读或写操作将自动进行，直到DMA传输完成。 阅读或写入顺序或替代宽字的能力有利地支持操作，以便在隔行视频显示的视频数据和用于逐行扫描显示的帧视频数据之间进行转换。

公开(公告)号：US20170070193A1

公开(公告)日：2017-03-09

申请号：US14948380

申请日：2015-11-22

Applicant: Ying-Zong Juang ,  Hann-Huei Tsai ,  Po-Chang Wu ,  Kuei-Cheng Lin ,  Chih-Yuan Yeh ,  Hwann-Kaeo Chiou

Inventor： Ying-Zong Juang ,  Hann-Huei Tsai ,  Po-Chang Wu ,  Kuei-Cheng Lin ,  Chih-Yuan Yeh ,  Hwann-Kaeo Chiou

IPC: H03F1/02 ,  H03F3/193 ,  H03F3/21 ,  H03F1/32

CPC classification number: H03F3/211 ,  H03F1/0261 ,  H03F1/3205 ,  H03F3/193 ,  H03F2200/432 ,  H03F2200/451 ,  H03F2201/3215 ,  H03F2203/21106

Abstract: The invention provides an RF power amplifier with post-distortion linearizer. The power amplifier includes a main amplifier, an auxiliary amplifier and a phase compensator. The first amplifier has a first input end and a first output end and operates in class A or AB. The auxiliary amplifier has a second input end and a second output end and operates in class B or C. The second output end connects the first output end to form a signal output end. The phase compensator has a third input end and a third output end and compensates a phase difference between the main and auxiliary amplifiers to make outputs of the two amplifiers opposite in phase. The third output end connects the second input end. The third input end connects the first input end to form a signal input end.

Abstract translation: 本发明提供一种具有后失真线性化的RF功率放大器。 功率放大器包括主放大器，辅助放大器和相位补偿器。 第一放大器具有第一输入端和第一输出端，​​并且在A或AB类中工作。 辅助放大器具有第二输入端和第二输出端，并且在B或C类中工作。第二输出端连接第一输出端以形成信号输出端。 相位补偿器具有第三输入端和第三输出端，并补偿主放大器和辅助放大器之间的相位差，使两个放大器的输出相位相反。 第三输出端连接第二输入端。 第三输入端连接第一输入端以形成信号输入端。

公开(公告)号：US06472922B1

公开(公告)日：2002-10-29

申请号：US09231940

申请日：1999-01-14

Applicant: Edward John Paluch, Jr. ,  Kuei-Cheng Lin

Inventor： Edward John Paluch, Jr. ,  Kuei-Cheng Lin

IPC: H03K300

CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/133

Abstract: The present invention comprises a system and method for flexibly distributing timing signals. Timing signals may require varying delays when connected, via circuit paths of varying propagation delays, to multiple circuit elements in order to preserve circuit synchronization. In one embodiment of the present invention, multiple clock signal generators are programmed to produce clock signals of differing time delays. This programming may be accomplished after the design and fabrication of the circuits utilizing the clock signals. These clock signals are then distributed, via circuit paths of varying propagation delays, to the multiple circuit elements.

Abstract translation: 本发明包括用于灵活地分配定时信号的系统和方法。 当通过不同传播延迟的电路路径连接时，定时信号可能需要变化的延迟到多个电路元件，以便保持电路同步。 在本发明的一个实施例中，多个时钟信号发生器被编程以产生不同时间延迟的时钟信号。 这种编程可以在使用时钟信号的电路的设计和制造之后完成。 这些时钟信号然后通过变化的传播延迟的电路路径被分配到多个电路元件。

公开(公告)号：US06223268B1

公开(公告)日：2001-04-24

申请号：US09229496

申请日：1999-01-08

Applicant: Edward John Paluch, Jr. ,  Kuei-Cheng Lin

Inventor： Edward John Paluch, Jr. ,  Kuei-Cheng Lin

IPC: G06F1204

CPC classification number: G06F12/04 ,  H04N5/85

Abstract: The present invention comprises an efficient system and method for writing specific bytes in a wide-word configured memory. A memory controller is configured to write from a wide-word databus to specific bytes in a wide-word addressed memory. The memory controller uses wide-word memory addresses which possess resolution capable of addressing specific bytes, and, in addition, data mask bytes which inhibit data write operations to those bytes in a wide-word which are not intended to be written in a given memory write operation. In one embodiment of the present invention, data mask bytes are created by shifting predetermined bit patterns to the right by an amount calculated by arithmetically combining bits in the wide-word memory address. A flexible individual address generating scheme allows memory write operations which do not depend upon the memory write operation's data boundaries being evenly aligned with the boundaries of wide-words.

Abstract translation: 本发明包括一种用于在宽字配置存储器中写入特定字节的有效系统和方法。 存储器控制器被配置为从宽字数据总线写入宽字寻址存储器中的特定字节。 存储器控制器使用具有能够寻址特定字节的分辨率的宽字存储器地址，另外还禁止数据掩码字节，这些数据掩码字节禁止数据写操作到宽字中的那些字节，这些字不是要写入给定存储器 写操作。 在本发明的一个实施例中，数据掩码字节是通过将预定位模式向右移动一个通过算术地组合宽字存储器地址中的位来计算的量来产生的。 灵活的单独地址生成方案允许不依赖于存储器写入操作的数据边界与宽字的边界均匀对齐的存储器写入操作。