公开(公告)号：US20080320375A1

公开(公告)日：2008-12-25

申请号：US12143114

申请日：2008-06-20

申请人： Kiyohide Hori ,  Hiroshi Benno ,  Takashi Ide

发明人： Kiyohide Hori ,  Hiroshi Benno ,  Takashi Ide

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： H04L1/0061 ,  H03M13/09 ,  H04L9/06 ,  H04L2209/34

摘要： To provide a data transmitting apparatus and the like capable of enhancing error detection accuracy without increasing a bandwidth unnecessarily used for the error detection performed on encrypted data and minimizing deterioration in sound quality of the data by effectively reducing noises in the transmission of the data through networks for cars and the like even though the data transmitting apparatus has been simply structured. The present invention makes it possible to perform error detection on audio data according to the sizes of encrypted blocks or packets using simple error check codes embedded in the audio data, or to perform error detection using a variation sequence of attribute information to be transmitted together with the audio data. In this case, output of the sound resulting from the audio data having an error is stopped.

摘要翻译： 为了提供能够提高错误检测精度的数据发送装置等，而不增加不必要地用于对加密数据进行的错误检测的带宽，并且通过有效减少通过网络传输数据的噪声来最小化数据的声音质量的劣化 对于汽车等，即使数据发送装置已经简单地构造。 本发明可以根据嵌入在音频数据中的简单错误校验码根据加密块或分组的大小对音频数据执行错误检测，或者使用将要传送的属性信息的变化序列进行错误检测 音频数据。 在这种情况下，停止由具有错误的音频数据产生的声音的输出。

公开(公告)号：US06990565B2

公开(公告)日：2006-01-24

申请号：US10396641

申请日：2003-03-25

申请人： Yoshihiro Tamura ,  Yutaka Tanase ,  Kiyohide Hori

发明人： Yoshihiro Tamura ,  Yutaka Tanase ,  Kiyohide Hori

IPC分类号： G06F12/10

CPC分类号： G06F12/06 ,  G06F12/0223

摘要： An address output apparatus capable of retaining a pre-extension upper compatibility of software post memory extension and of accessing separated RAM areas by consecutive addresses, without needing to alter CPU architecture. The address output apparatus includes an address conversion circuit 20 that allots to a RAM 30 a basic RAM area and a first area, being one of two area obtained by dividing an extension RAM area, allots to a RAM 50 a second area, being an area other than the first area of the extension RAM area, and converts logical address signals designated by a CPU 10 to physical address signals based on a state of the allotting.

摘要翻译： 一种地址输出装置，其能够保持软件后存储器扩展的预扩展上兼容性并且通过连续地址访问分离的RAM区域，而不需要改变CPU架构。 地址输出装置包括地址转换电路20，其向RAM30分配基本RAM区域和作为通过分割扩展RAM区域而获得的两个区域之一的第一区域，分配给RAM 50第二区域，第二区域 除了扩展RAM区域的第一区域之外，并且基于分配的状态将由CPU 10指定的逻辑地址信号转换为物理地址信号。