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    Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data
    1.
    发明授权
    Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data 有权
    将专用搜索寄存器和专用状态机寄存器与相关执行硬件集成在一起的可编程处理器设备支持快速应用规则集到数据

    公开(公告)号：US07464254B2

    公开(公告)日：2008-12-09

    申请号：US10755188

    申请日：2004-01-08

    Applicant: Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

    Inventor： Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

    IPC: G06F7/00

    CPC classification number: G06F17/30982 ,  G06F7/00 ,  G06F17/30985

    Abstract: A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.

    Abstract translation: 公开了一种规则处理器及其使用方法。 在一个实施例中，规则处理器包括通用寄存器文件，提供指令的指令定序器，耦合到通用寄存器文件的解码器，以对由指令定序器指定的一组指令进行解码;以及状态机单元， 解码器，并且具有状态机寄存器，用于存储耦合到状态机寄存器的一个或多个状态机和状态机执行硬件，以响应于执行该组指令中的一个或多个并且基于来自一个指令的信息来评估一个或多个状态机 或解码器和通用寄存器文件两者。

    Methods and apparatuses for evaluation of regular expressions of arbitrary size
    2.
    发明申请
    Methods and apparatuses for evaluation of regular expressions of arbitrary size 失效
    用于评估任意大小的正则表达式的方法和装置

    公开(公告)号：US20050012521A1

    公开(公告)日：2005-01-20

    申请号：US10755048

    申请日：2004-01-08

    Applicant: Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Arora

    Inventor： Harshvardhan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Arora

    IPC: G05B19/042 ,  G05B19/045 ,  G06F7/38

    CPC classification number: G06F7/00 ,  G06F17/30985

    Abstract: Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

    Abstract translation: 本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。 本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。 对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。 对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。 对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。

    Methods and apparatuses for evaluation of regular expressions of arbitrary size
    4.
    发明授权
    Methods and apparatuses for evaluation of regular expressions of arbitrary size 失效
    用于评估任意大小的正则表达式的方法和装置

    公开(公告)号：US07085918B2

    公开(公告)日：2006-08-01

    申请号：US10755048

    申请日：2004-01-08

    Applicant: Harshvardan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

    Inventor： Harshvardan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

    IPC: G06F15/00 ,  G06F17/28

    CPC classification number: G06F7/00 ,  G06F17/30985

    Abstract: Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

    Abstract translation: 本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。 本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。 对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。 对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。 对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。

    Processor utilizing a template field for encoding instruction sequences in a wide-word format
    5.
    发明授权
    Processor utilizing a template field for encoding instruction sequences in a wide-word format 失效
    处理器利用模板字段来编码宽字格式的指令序列

    公开(公告)号：US5922065A

    公开(公告)日：1999-07-13

    申请号：US949279

    申请日：1997-10-13

    Applicant: James M. Hull ,  Kent Fielden ,  Hans Mulden ,  Harshvardhan Sharangpani

    Inventor： James M. Hull ,  Kent Fielden ,  Hans Mulden ,  Harshvardhan Sharangpani

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

    CPC classification number: G06F9/3885 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3853

    Abstract: A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.

    Abstract translation: 具有大寄存器文件的处理器利用模板字段来编码长指令字格式的一组最有用的指令序列。 处理器的指令集包括作为多种不同指令类型之一的指令。 处理器的执行单元类似地分类为不同类型，其中每个指令类型可以在一个或多个执行单元类型上执行。 这些指令被分组在128位大小和对齐的容器中，称为捆绑包，每个包包括多个指令槽和模板字段，其指定指令槽与执行单元类型的映射。

    Storing predicted branch target address in different storage according to importance hint in branch prediction instruction
    6.
    发明授权
    Storing predicted branch target address in different storage according to importance hint in branch prediction instruction 失效
    根据分支预测指令的重要性提示将预测的分支目标地址存储在不同的存储器中

    公开(公告)号：US06178498B1

    公开(公告)日：2001-01-23

    申请号：US08993450

    申请日：1997-12-18

    Applicant: Harshvardhan Sharangpani ,  Kent Fielden

    Inventor： Harshvardhan Sharangpani ,  Kent Fielden

    IPC: G06F938

    CPC classification number: G06F9/3806 ,  G06F9/3005 ,  G06F9/3844 ,  G06F9/3846

    Abstract: A branch prediction instruction is provided that includes hint information for indicating a storage location for associated branch prediction information in a hierarchy of branch prediction storage structures. When the hint information is in a first state, branch prediction information is stored in a first structure that provides single cycle access to the stored information. When the hint information is in a second state, the branch prediction information is stored in a second structure that provides slower access to the stored information.

    Abstract translation: 提供了一种分支预测指令，其包括用于指示分支预测存储结构的层级中的相关联的分支预测信息的存储位置的提示信息。 当提示信息处于第一状态时，分支预测信息被存储在提供对存储的信息的单周期访问的第一结构中。 当提示信息处于第二状态时，分支预测信息被存储在提供对存储的信息的较慢访问的第二结构中。

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