公开(公告)号：US06173379B2

公开(公告)日：2001-01-09

申请号：US08645653

申请日：1996-05-14

Applicant: Mircea Poplingher ,  Wenliang Chen ,  Ganesh Suryanarayanan ,  Wayne W. Chen ,  Roger Y. Lo

Inventor： Mircea Poplingher ,  Wenliang Chen ,  Ganesh Suryanarayanan ,  Wayne W. Chen ,  Roger Y. Lo

IPC: G06F1300

CPC classification number: G11C11/417

Abstract: A memory device including an array of memory cells and a method for copying information within the memory device. Each memory cell includes a first memory sub-cell and a second memory sub-cell. Each memory cell also includes a device that copies information from the first memory sub-cell into the second memory sub-cell. Each memory cell may include a static random access memory (SRAM) cell and may utilize tri-state inverters to make overwriting information easier and reduce power consumption. Each memory cell may also include a second copy device that allows information to be copied from the second memory sub-cell to the first memory sub-cell. The memory device may be provided in a register file of a microprocessor to copy information from an architectural branch register (ABR) file to a speculative branch register (SBR) file.

Abstract translation: 包括存储器单元阵列的存储器件和用于在存储器件内复制信息的方法。 每个存储单元包括第一存储器子单元和第二存储器子单元。 每个存储器单元还包括将信息从第一存储器子单元复制到第二存储器子单元的设备。 每个存储单元可以包括静态随机存取存储器（SRAM）单元，并且可以利用三态反相器来使得覆盖信息更容易并且降低功耗。 每个存储器单元还可以包括允许将信息从第二存储器子单元复制到第一存储器子单元的第二复制设备。 存储器件可以设置在微处理器的寄存器文件中，以将信息从架构分支寄存器（ABR）文件复制到推测性分支寄存器（SBR）文件。

公开(公告)号：US5815700A

公开(公告)日：1998-09-29

申请号：US576954

申请日：1995-12-22

Applicant: Mircea Poplingher ,  Tse-Yu Yeh ,  Wenliang Chen

Inventor： Mircea Poplingher ,  Tse-Yu Yeh ,  Wenliang Chen

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3844

Abstract: A branch prediction system is described for use within a microprocessor having an instruction cache capable of storing two or more instructions per cache line. Each entry of a branch prediction table (BPT) includes a value identifying whether at least one other instruction within a common cache line contains a branch. The value is referred to herein as a multiple-B bit value. The multiple-B bit value is examined by branch prediction logic while one branch prediction is being performed to determine whether a second branch prediction can be initiated for another branch within the same cache line. In one implementation, the multiple-B bit of one BPT entry is examined following a hit. A branch prediction for the entry generating a hit is initiated. Simultaneously, the BPT is reaccessed to search for an entry corresponding to another instruction within the same cache line if the multiple-B bit for the first entry was set. If the second entry is found, a secondary branch prediction is initiated. Eventually, the first branch prediction is output. If the first branch prediction is Not Taken, then the second branch prediction is output during the next clock cycle. If the first branch prediction is Taken, then the second branch prediction may be aborted as it is not needed. Method and apparatus embodiments of the invention are described.

Abstract translation: 描述了一种在具有每个高速缓存行存储两个或多个指令的指令高速缓存器的微处理器内使用的分支预测系统。 分支预测表（BPT）的每个条目包括标识公共高速缓存行中的至少一个其他指令是否包含分支的值。 该值在本文中称为多B位值。 通过分支预测逻辑检查多个B比特值，同时执行一个分支预测以确定是否可以针对同一高速缓存行内的另一个分支启动第二分支预测。 在一个实现中，在命中之后检查一个BPT条目的多个B位。 开始生成命中的条目的分支预测。 同时，如果设置了第一个条目的多个B位，则BPT被重新访问以搜索与同一高速缓存行内的另一个指令相对应的条目。 如果找到第二个条目，则启动辅助分支预测。 最终输出第一个分支预测。 如果第一分支预测未被采用，则在下一个时钟周期期间输出第二分支预测。 如果采用第一分支预测，那么第二分支预测可能因不需要而中止。 描述本发明的方法和设备实施例。

公开(公告)号：US5742804A

公开(公告)日：1998-04-21

申请号：US685607

申请日：1996-07-24

Applicant: Tse-Yu Yeh ,  Mircea Poplingher ,  Kent G. Fielden ,  Hans Mulder ,  Rajiv Gupta ,  Dale Morris ,  Michael Schlansker

Inventor： Tse-Yu Yeh ,  Mircea Poplingher ,  Kent G. Fielden ,  Hans Mulder ,  Rajiv Gupta ,  Dale Morris ,  Michael Schlansker

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/3836 ,  G06F9/3846

Abstract: A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

Abstract translation: 在程序指令序列的执行中减少指令提取损失的处理器和方法包括在分支之前的位置处插入到程序中的分支预测指令。 分支预测指令具有指定可能被采用或未被采用的分支的操作​​码，并且还指定分支的目标地址。 从目标地址开始的目标指令块被预取到处理器的指令高速缓存中，使得指令在程序中遇到分支的点之前可用于执行。 操作码还指定了目标指令块的大小的指示，以及由分支预测指令导致目标的程序序列中的路径的跟踪向量，以更好地利用有限的存储器带宽。

公开(公告)号：US20050066153A1

公开(公告)日：2005-03-24

申请号：US10461782

申请日：2003-06-12

Applicant: Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

Inventor： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

IPC: G06F9/32 ,  G06F9/38 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/3806 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3844 ,  G06F9/3846

Abstract: A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

Abstract translation: 使用分支预测指令和相关联的分支指令来处理分支操作。 分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。 当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。 分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

公开(公告)号：US6092188A

公开(公告)日：2000-07-18

申请号：US348406

申请日：1999-07-07

Applicant: Michael P. Corwin ,  Tse-Yu Yeh ,  Mircea Poplingher ,  Carl C. Scafidi

Inventor： Michael P. Corwin ,  Tse-Yu Yeh ,  Mircea Poplingher ,  Carl C. Scafidi

IPC: G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC classification number: G06F9/3804 ,  G06F9/322 ,  G06F9/3846

Abstract: A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.

Abstract translation: 一种具有指令集的处理器架构，具有预测指令，所述预测指令提供静态预测信息和静态预测的目标地址给处理器用于分支指令。 处理器对预测指令进行解码以获得包括预测目标地址和参考指令地址的相关联的地址对，并且当获取和解码的分支指令具有指令地址时，获取具有与预测目标地址匹配的指令地址的预测目标指令 匹配引用的指令地址。

公开(公告)号：US6021489A

公开(公告)日：2000-02-01

申请号：US885394

申请日：1997-06-30

Applicant: Mircea Poplingher

Inventor： Mircea Poplingher

IPC: G06F9/38

CPC classification number: G06F9/3879 ,  G06F9/3844 ,  G06F9/3846

Abstract: A microprocessor that includes first and second Instruction Fetch Units (IFU) coupled therebetween is provided. The first IFU implements a first Instruction Set Architecture (ISA). The second IFU implements a second ISA. The microprocessor further includes a shared branch prediction unit coupled to the first and second IFU. The shared branch prediction unit stores prediction-related information. In the same paragraph, the present invention also provides a method of performing branch prediction. According to this method, an instruction pointer is provided to a branch prediction unit that stores information shared by first and second IFU. The instruction pointer is generated by one of the first and second IFU that is active. Determination is made of whether an instruction corresponding to the instruction pointer, provided to the branch prediction unit, is a branch instruction, and if so, it is determined if a branch is predicted taken. If the branch instruction is predicted taken, target address corresponding to the branch instruction is provided to the first and second IFU.

Abstract translation: 提供了包括耦合在其间的第一和第二指令提取单元（IFU）的微处理器。 第一个IFU实现了第一个指令集架构（ISA）。 第二个IFU实现了第二个ISA。 微处理器还包括耦合到第一和第二IFU的共享分支预测单元。 共享分支预测单元存储预测相关信息。 在同一段中，本发明还提供了一种执行分支预测的方法。 根据该方法，向存储由第一和第二IFU共享的信息的分支预测单元提供指令指针。 指令指针由有效的第一和第二IFU之一产生。 确定提供给分支预测单元的与指令指针相对应的指令是否是分支指令，如果是，则确定是否预测分支。 如果预测分支指令，则将对应于分支指令的目标地址提供给第一和第二IFU。

公开(公告)号：US5802602A

公开(公告)日：1998-09-01

申请号：US785199

申请日：1997-01-17

Applicant: Monis Rahman ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Wenliang Chen

Inventor： Monis Rahman ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Wenliang Chen

IPC: G06F9/38 ,  G06F12/08 ,  G06F1/00

CPC classification number: G06F9/3806 ,  G06F12/0864

Abstract: Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the corresponding entries in each of the ways to the related data units, so that related data units are stored in a common set of entries. Accordingly, the related data units will be simultaneously outputted from the set-associative cache memory, and are thus concurrently available for processing. The invention may find application in allocating entries of a common set in a branch prediction table (BPT) to branch prediction information for related branch instructions.

Abstract translation: 公开了用于在集合关联高速缓冲存储器内分配条目的分配电路。 集合关联高速缓冲存储器包括N个方式，每个路径具有M个条目和N个路径中的每一个中的相应条目，构成一组条目。 分配电路具有通过识别相关数据单元可以从高速缓冲存储器连续读取的概率来识别相关数据单元的第一电路。 分配电路内的第二电路以相应数据单元的每一种方式分配相应的条目，使得相关的数据单元被存储在一组共同的条目中。 因此，相关数据单元将从集合关联高速缓冲存储器同时输出，因此同时可用于处理。 本发明可以在将分支预测表（BPT）中的公共集合的条目分配给用于相关分支指令的分支预测信息的应用中。

公开(公告)号：US06611910B2

公开(公告)日：2003-08-26

申请号：US09169868

申请日：1998-10-12

Applicant: Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent G. Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

Inventor： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent G. Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

IPC: G06F930

CPC classification number: G06F9/3806 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3844 ,  G06F9/3846

Abstract: A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

Abstract translation: 使用分支预测指令和相关联的分支指令来处理分支操作。 分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。 当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。 分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

公开(公告)号：US06438682B1

公开(公告)日：2002-08-20

申请号：US09169866

申请日：1998-10-12

Applicant: Dale Morris ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Michael P. Corwin ,  Wenliang Chen

Inventor： Dale Morris ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Michael P. Corwin ,  Wenliang Chen

IPC: G06F932

CPC classification number: G06F9/325

Abstract: A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.

Abstract translation: 提供循环分支预测系统以预测循环的最终迭代并将相关联的获取模块修复到适当的目标地址。 环路预测系统包括计数器和结束循环（EOL）模块。 在一种模式下，计数器跟踪正在进行的循环分支。 当检测到终止条件时，计数器切换到第二模式以跟踪仍然发布的循环分支的数量。 EOL模块将仍然要发出的环路分支数与一个或多个阈值进行比较，并在检测到匹配时产生一个恢复信号。

公开(公告)号：US5987599A

公开(公告)日：1999-11-16

申请号：US827296

申请日：1997-03-28

Applicant: Mircea Poplingher ,  Tse-Yu Yeh

Inventor： Mircea Poplingher ,  Tse-Yu Yeh

IPC: G06F9/38

CPC classification number: G06F9/3806

Abstract: A processor that includes an execution pipeline that executes a programmed flow of instructions is provided. The processor also includes an instruction pointer generator configured to generate an instruction pointer. Furthermore, the processor includes a branch prediction circuit configured to receive the instruction pointer. In response to the instruction pointer, the branch prediction circuit is configured to determine if an instruction corresponding to the instruction pointer includes a branch that is predicted taken and if so to provide to said execution pipeline a target instruction corresponding to said instruction. The branch prediction circuit provides to the execution pipeline at least one target instruction corresponding to the instruction corresponding to the instruction pointer.

Abstract translation: 提供了一种处理器，其包括执行编程的指令流程的执行流水线。 处理器还包括被配置为生成指令指针的指令指针发生器。 此外，处理器包括被配置为接收指令指针的分支预测电路。 响应于指令指针，分支预测电路被配置为确定与指令指针相对应的指令是否包括预测的分支，并且如果是，则向所述执行流水线提供与所述指令相对应的目标指令。 分支预测电路向执行流水线提供对应于与指令指针相对应的指令的至少一个目标指令。