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    Mechanism for handling explicit writeback in a cache coherent multi-node architecture
    2.
    发明授权
    Mechanism for handling explicit writeback in a cache coherent multi-node architecture 有权
    在缓存一致多节点架构中处理显式回写的机制

    公开(公告)号：US07167957B2

    公开(公告)日：2007-01-23

    申请号：US10896151

    申请日：2004-07-20

    申请人： Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar

    发明人： Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831 ,  G06F12/0804 ,  G06F12/0828

    摘要： A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

    摘要翻译： 描述了一种用于在高速缓存相关多节点架构中处理显式回写的机制的方法和装置。 在一个实施例中，本发明是一种方法。 该方法包括在相干存储器系统中接收与第一行数据有关的读取请求。 该方法还包括在接收到读取请求的同时接收与第一行数据相关的写入请求。 该方法还包括检测读请求和写请求都与第一行相关。 该方法还包括确定读和写请求的哪个请求应首先进行。 此外，该方法包括完成应该首先进行的读取和写入请求的请求。

    Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system
    3.
    发明授权
    Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system 有权
    用于将有序输入/输出事务流水线分配存储器，高速缓存一致的多处理器系统中的相干存储器的方法和装置

    公开(公告)号：US07124252B1

    公开(公告)日：2006-10-17

    申请号：US09643380

    申请日：2000-08-21

    申请人： Manoj Khare ,  Akhilesh Kumar ,  Lily P. Looi ,  Kenneth C. Creta

    发明人： Manoj Khare ,  Akhilesh Kumar ,  Lily P. Looi ,  Kenneth C. Creta

    IPC分类号： G06F13/14

    CPC分类号： G06F12/0862 ,  G06F12/0831 ,  G06F12/0835

    摘要： An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.

    摘要翻译： 用于将有序输入/输出事务流水线分配到分布式存储器，高速缓存一致的多处理器系统中的相干存储器的方法。 响应于来自指向分布式相干存储器的输入/输出总线的事务，预取引擎从分布式相干存储器预取数据。 输入/输出相干缓存缓冲器接收预取数据，并与分布式，相干存储器和系统中的其他高速缓存代理保持一致。

    Methods and apparatuses for evaluation of regular expressions of arbitrary size
    4.
    发明授权
    Methods and apparatuses for evaluation of regular expressions of arbitrary size 失效
    用于评估任意大小的正则表达式的方法和装置

    公开(公告)号：US07085918B2

    公开(公告)日：2006-08-01

    申请号：US10755048

    申请日：2004-01-08

    申请人： Harshvardan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

    发明人： Harshvardan Sharangpani ,  Manoj Khare ,  Kent Fielden ,  Rajesh Patil ,  Judge Kennedy Arora

    IPC分类号： G06F15/00 ,  G06F17/28

    CPC分类号： G06F7/00 ,  G06F17/30985

    摘要： Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

    摘要翻译： 本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。 本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。 对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。 对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。 对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。

    Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture
    5.
    发明授权
    Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture 有权
    用于将已知事务长度的I / O事务处理到缓存一致多节点体系结构中的相干内存的机制

    公开(公告)号：US06976129B2

    公开(公告)日：2005-12-13

    申请号：US10261944

    申请日：2002-09-30

    申请人： Kenneth C. Creta ,  Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar

    发明人： Kenneth C. Creta ,  Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0813 ,  Y10S707/99952

    摘要： A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.

    摘要翻译： 描述了一种用于处理具有已知事务长度的I / O事务的机制的方法和装置，用于缓存相关多节点架构中的相干存储器。 在一个实施例中，本发明是一种方法。 该方法包括接收对数据线的当前副本的请求。 该方法还包括在高速缓存相干多节点系统内找到数据线。 该方法还包括复制数据线而不干扰与数据线相关联的状态。 该方法还包括响应于该请求提供数据线的副本。 该方法还包括基于事务的已知事务长度来确定数据行是否是事务的最后数据行。

    Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line
    6.
    发明授权
    Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line 失效
    响应于读取或窥探修改的高速缓存行启动隐式回写的机制

    公开(公告)号：US06859864B2

    公开(公告)日：2005-02-22

    申请号：US09752576

    申请日：2000-12-29

    申请人： Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar ,  Kenneth C. Creta

    发明人： Manoj Khare ,  Lily P. Looi ,  Akhilesh Kumar ,  Kenneth C. Creta

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0813 ,  G06F12/0804 ,  G06F12/082 ,  G06F12/0831

    摘要： A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.

    摘要翻译： 描述了一种用于在实现基于窥探的体系结构的分布式共享存储器环境中提供隐式回写的方法和装置。 请求节点向基于窥探的架构控制器交换机提交单个读取请求。 该交换机识别除请求节点之外的另一节点和所需数据的归属节点具有该数据的副本。 交换机将请求引导到不是主节点的响应节点。 已经修改了数据的响应节点向交换机提供了一个单一的响应，该响应使交换机能够更新归属节点处的数据并且回答请求节点。 在家庭节点处的数据更新完成，而不从请求节点接收到明确的写入指令。

    Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems
    8.
    发明授权
    Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems 失效
    用于在计算机存储器子系统中有效读取指令代码数据的方法和装置

    公开(公告)号：US5367657A

    公开(公告)日：1994-11-22

    申请号：US955042

    申请日：1992-10-01

    申请人： Manoj Khare ,  Sudarshan B. Cadambi

    发明人： Manoj Khare ,  Sudarshan B. Cadambi

    IPC分类号： G06F9/38 ,  G06F12/02 ,  G06F9/26 ,  G06F9/34 ,  G06F13/00

    CPC分类号： G06F9/3814 ,  G06F12/0215 ,  G06F9/3802

    摘要： A memory subsystem and method are disclosed in which instruction code read-prefetching is implemented in the memory subsystem itself. A single-line read-prefetch buffer is implemented in the memory subsystem. A memory controller includes an address buffer for read-prefetches, and a memory datapath includes a data buffer for read-prefetches. Smart read-prefetching is used in which only code(instruction) reads are prefetched, taking advantage of the sequentiality of code (instruction) type data as well as the page mode feature of dynamic random access memories.

    摘要翻译： 公开了一种存储器子系统和方法，其中在存储器子系统本身中实现了指令代码读取预取。 在内存子系统中实现单行读取预取缓冲区。 存储器控制器包括用于读取预取的地址缓冲器，并且存储器数据路径包括用于读取预取的数据缓冲器。 使用智能读取预取，其中仅使用代码（指令）读取，利用代码（指令）类型数据的顺序性以及动态随机存取存储器的页面模式特征。