发明授权
US06976129B2 Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture
有权
用于将已知事务长度的I / O事务处理到缓存一致多节点体系结构中的相干内存的机制
- 专利标题: Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture
- 专利标题(中): 用于将已知事务长度的I / O事务处理到缓存一致多节点体系结构中的相干内存的机制
-
申请号: US10261944申请日: 2002-09-30
-
公开(公告)号: US06976129B2公开(公告)日: 2005-12-13
- 发明人: Kenneth C. Creta , Manoj Khare , Lily P. Looi , Akhilesh Kumar
- 申请人: Kenneth C. Creta , Manoj Khare , Lily P. Looi , Akhilesh Kumar
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F12/08
摘要:
A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.
公开/授权文献
信息查询