公开(公告)号：US4262351A

公开(公告)日：1981-04-14

申请号：US943263

申请日：1978-09-15

Applicant: Shigeru Morokawa ,  Fukuo Sekiya ,  Yukio Hashimoto ,  Yasushi Nomura ,  Keiichiro Koga

Inventor： Shigeru Morokawa ,  Fukuo Sekiya ,  Yukio Hashimoto ,  Yasushi Nomura ,  Keiichiro Koga

IPC: G04G15/00 ,  G04C3/00 ,  G04G3/02 ,  G04G5/04 ,  G04G9/00 ,  G04G11/00 ,  G04G13/02 ,  G04G17/08 ,  G04G99/00 ,  G04B23/02 ,  G04C21/16

CPC classification number: G04G99/006 ,  G04C3/005 ,  G04G11/00 ,  G04G13/025 ,  G04G5/04

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the time base signal to provide a relatively low frequency time unit signal, timing signals, and a plurality of word pulses indicative of plurality of data words representing time data concerning the current time, and a set of additional data other than the time data. A primary register is arranged to store the time data and the additional data, and display means displays the time data and the additional data. An external control member is adapted to provide an input signal when actuated, and an indexing signal is generated in response to the input signal. A secondary register is arranged to store a plurality of sets of additional data and is operable to transfer each set of additional data to the primary register in a sequential manner as the first mentioned set of additional data in response to the indexing signal, whereupon each of the sets of additional data is sequentially displayed by the display means.

Abstract translation: 电子钟表包括用于提供相对高频时基信号的频率供应器，响应于时基信号的频率转换器，提供相对低频的时间单位信号，定时信号以及表示多个数据的多个字脉冲 表示与当前时间有关的时间数据的单词，以及除了时间数据之外的一组附加数据。 主寄存器被设置为存储时间数据和附加数据，并且显示装置显示时间数据和附加数据。 外部控制构件适于在致动时提供输入信号，并且响应于输入信号产生分度信号。 次级寄存器被布置为存储多组附加数据，并且可操作以响应于索引信号以顺序方式将每组附加数据传送到主寄存器作为第一附加数据组，因此， 显示装置依次显示附加数据组。

公开(公告)号：US4694455A

公开(公告)日：1987-09-15

申请号：US772504

申请日：1985-09-04

Applicant: Keiichiro Koga

Inventor： Keiichiro Koga

IPC: H03M13/00 ,  H03M13/15 ,  G06F11/12

CPC classification number: H03M13/15

Abstract: In an error correction code decoding system using BCH (Bose-Chaudhuri-Hocquenghem) code for correcting error bits in input data Y=(y.sub.1, y.sub.2, - - - , y.sub.n) having the steps of obtaining syndrome S=(S.sub.1, S.sub.2, - - , S.sub.n) through calculation of YH.sup.t, where H is a parity check matrix, obtaining determinant Q.sub.t (equation 6) which has elements of said syndrome S=(S.sub.1, S.sub.2, - - - , S.sub.n), and Q determinant which is provided by deleting some rows and columns including specified diagonal elements of said Q.sub.t determinant, determining coefficients of error locator polynominal by using said Q determinant, and solving said error locator polynomial, the improvement that said Q determinant is calculated by Q determinant storage means for storing the calculated Q determinant, and calculation means for providing accumulation of product (equation 11) of Q determinant in said storage means and square of said syndrome, and updating said storage means in order to simplify decoding equipment. Said Q.sub.t determinant and Q determinant may be replaced by Q polynomial, and the square of the syndrome by the syndrome itself.

Abstract translation: 在使用BCH（Bose-Chaudhuri-Hocquenghem）码校正输入数据Y =（y1，y2， - - ，yn）中的错误位的纠错码解码系统中，具有获得S =（S1，S2， - - ，Sn），其中H是奇偶校验矩阵，获得具有所述综合征S =（S1，S2， - - - ，Sn）的元素的决定因素Qt（等式6）和Q 通过删除包括所述Qt行列式的指定对角线元素的一些行和列来提供，通过使用所述Q行列式确定误差定位器多项式的系数，并求解所述误差定位多项式，所述Q行列式由Q行列式存储装置计算， 计算出的Q行列式，以及用于在所述存储装置中提供Q行列式的乘积（等式11）的积累和所述校正子的平方的计算装置，并且更新所述存储装置以简化解码设备。 所述Qt行列式和Q行列式可以由Q多项式代替，综合征本身的平方和。

公开(公告)号：US4748622A

公开(公告)日：1988-05-31

申请号：US890235

申请日：1986-07-29

Applicant: Takuro Muratani ,  Tatsuo Watanabe ,  Michihisa Ohkawa ,  Keiichiro Koga

Inventor： Takuro Muratani ,  Tatsuo Watanabe ,  Michihisa Ohkawa ,  Keiichiro Koga

IPC: H04B7/15 ,  H04B7/185 ,  H04J3/06

CPC classification number: H04B7/18578 ,  H04J3/0626

Abstract: A satellite communication among a plurality of small earth stations (very small aperture terminal;VSAT) through a satellite is performed by using a relay earth station which has higher power than a small earth station. A signal goes from an originating small earth station to a destination small earth station, through a satellite, a relay earth station, and a satellite by using two hops propagation. Communication is carried out in digital form. The relay earth station regenerates digital signals from small earth stations. In the process of the regeneration of the digital signals, the error correction technique is applied to reduce the error rate, and a frequency compensation technique is also employed. Thus, a small simple earth station can provide high quality of communication with high C/N. A reference clock signal for operating a small earth station is derived from a reception signal from a satellite.

Abstract translation: 通过使用具有比小地球站更高的功率的中继地球站，通过卫星进行多个小地球站（非常小的孔径终端; VSAT）之间的卫星通信。 信号通过卫星，中继地球站和卫星通过使用两个跳传播从原始的小地球站到达目的地小地球站。 沟通以数字形式进行。 中继地球站从小地球站再生数字信号。 在数字信号的再生过程中，采用纠错技术来降低误码率，并采用频率补偿技术。 因此，一个小型简单的地球站可以提供高C / N的高质量通信。 用于操作小型地球站的参考时钟信号是从卫星的接收信号导出的。

公开(公告)号：US4441826A

公开(公告)日：1984-04-10

申请号：US430569

申请日：1982-09-30

Applicant: Shigeru Morokawa ,  Keiichiro Koga

Inventor： Shigeru Morokawa ,  Keiichiro Koga

IPC: G04C10/04 ,  G04G3/02 ,  G04G9/00 ,  G05F3/24 ,  H03B5/32 ,  G04B1/00 ,  G05F1/56 ,  H03K3/01

CPC classification number: G04C10/04 ,  G04G3/022 ,  G04G9/0047 ,  G05F3/245 ,  G05F3/247 ,  Y10S331/03

Abstract: An electronic timepiece having voltage regulation, temperature detection and battery voltage detection means provided on the same integrated circuit as is used for timekeeping circuitry, and having external terminals for stepwise weighted adjustment of timekeeping gain/loss.

Abstract translation: 具有电压调节，温度检测和电池电压检测装置的电子钟表，设置在与计时电路相同的集成电路上，并具有用于逐步加权调整计时增益/损耗的外部端子。

公开(公告)号：US4302829A

公开(公告)日：1981-11-24

申请号：US943260

申请日：1978-09-15

Applicant: Shigeru Morokawa ,  Fukuo Sekiya ,  Yukio Hashimoto ,  Yasushi Nomura ,  Keiichiro Koga

Inventor： Shigeru Morokawa ,  Fukuo Sekiya ,  Yukio Hashimoto ,  Yasushi Nomura ,  Keiichiro Koga

IPC: G04G15/00 ,  G04C3/00 ,  G04G3/02 ,  G04G5/04 ,  G04G9/00 ,  G04G11/00 ,  G04G13/02 ,  G04G17/08 ,  G04G99/00 ,  G04C19/00 ,  G04F5/00

CPC classification number: G04G99/006 ,  G04C3/005 ,  G04G11/00 ,  G04G13/025 ,  G04G5/04

Abstract: An electronic timepiece includes a primary timepiece circuit unit including a frequency supply for providing a relatively high frequency signal, a frequency converter responsive to the relatively high frequency signal to provide a relatively low frequency time unit signal, timing signals, and a plurality of word pulses indicative of a plurality of data words representing time data concerning the current time, and a set of additional data other than the time data, a timekeeping register arranged to store the time data and the additional data, and display elements for displaying the time data and the additional data. A secondary timepiece circuit unit includes a register arranged to store the additional data to be transferred to the timekeeping register.

Abstract translation: 电子钟表包括主时钟电路单元，其包括用于提供相对较高频率信号的频率供应，响应于相对高频信号的频率转换器，提供相对低频的时间单位信号，定时信号和多个字脉冲 指示表示与当前时间有关的时间数据的多个数据字，以及除了时间数据之外的一组附加数据，布置成存储时间数据和附加数据的计时寄存器以及用于显示时间数据的显示元件，以及 附加数据。 次级钟表电路单元包括寄存器，其被布置为存储要传送到计时寄存器的附加数据。

公开(公告)号：US4236241A

公开(公告)日：1980-11-25

申请号：US943265

申请日：1978-09-15

Applicant: Shigeru Morokawa ,  Fukuo Sekiya ,  Yukio Hashimoto ,  Yasushi Nomura ,  Keiichiro Koga

Inventor： Shigeru Morokawa ,  Fukuo Sekiya ,  Yukio Hashimoto ,  Yasushi Nomura ,  Keiichiro Koga

IPC: G04G15/00 ,  G04C3/00 ,  G04G3/02 ,  G04G5/04 ,  G04G9/00 ,  G04G11/00 ,  G04G13/02 ,  G04G17/08 ,  G04G99/00 ,  G04C19/00 ,  G04C17/00

CPC classification number: G04G99/006 ,  G04C3/005 ,  G04G11/00 ,  G04G13/025 ,  G04G5/04

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the relatively high frequency time base signal to provide a timing signal, a clock signal, and a time unit signal. A timekeeping circuit is responsive to the time unit signal to provide a time information signal, and at least one of the timing signal, clock signal, and time information signal is chopped into periodic bursts to effect transfer of the at least one of the timing signal, clock signal, and time information signal from one part to another part in the timepiece. The time in response to the time information signal is displayed.

Abstract translation: 电子表包括用于提供相对较高频率的时基信号的频率电源，响应于相对高频时基信号的频率转换器，以提供定时信号，时钟信号和时间单位信号。 计时电路响应于时间单位信号以提供时间信息信号，并且将定时信号，时钟信号和时间信息信号中的至少一个斩波成周期脉冲串，以实现定时信号中的至少一个的传输 ，时钟信号和时间信息信号从钟表中的一个部分到另一个部分。 显示响应时间信息信号的时间。

公开(公告)号：US5345506A

公开(公告)日：1994-09-06

申请号：US70730

申请日：1993-06-02

Applicant: Hideki Tsubakiyama ,  Masayoshi Oohashi ,  Keiichiro Koga

Inventor： Hideki Tsubakiyama ,  Masayoshi Oohashi ,  Keiichiro Koga

IPC: G09C1/00 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/32 ,  H04K1/00

CPC classification number: H04L9/0847 ,  H04L9/3273 ,  H04L2209/80

Abstract: A communication network and its user i has a device for implementing a common key cryptosystem, an identifier of the user i represented by ID.sub.i which is made public in the network, an authentication key of a user i represented by S.sub.i is known only to the network and the user i and these identifiers and authentication keys of all the users are stored in a database of the network. Data for authentication and encrypted data of a cipher key for the subsequent privacy communication are sent from the network to the user, the user presents his identifier (ID) to the network, after which up to three interactions take place between the network and the user to perform the required authentications and distribution of the cipher key.

Abstract translation: 通信网络及其用户i具有用于实现公共密钥密码系统的设备，由网络中公开的IDi表示的用户i的标识符，由Si表示的用户i的认证密钥仅对网络是已知的 并且所有用户的用户i和这些标识符和认证密钥存储在网络的数据库中。 用于后续隐私通信的密码密钥的认证数据和加密数据从网络发送给用户，用户向网络呈现他的标识符（ID），之后在网络和用户之间进行三次交互 执行密码密钥的所需认证和分发。

公开(公告)号：US4797887A

公开(公告)日：1989-01-10

申请号：US921517

申请日：1986-10-22

Applicant: Norikazu Yamasaki ,  Keiichiro Koga

Inventor： Norikazu Yamasaki ,  Keiichiro Koga

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/39

CPC classification number: H03M13/39

Abstract: A sequential decoding of a convolutionally encoded sequence has been proposed. Decoding is carried out by extending paths along the branches of code-tree over plural tree levels at a time and calculating likelihood (metric) of the extended paths referring to the received sequence. Decoding is terminated when it proceeds to a node belonging to the last tree level of a data block. Then, one of the extended sequences associated with a node located at the last tree level which has the largest metric is output as a decoded sequence.

Abstract translation: 已经提出了卷积编码序列的顺序解码。 一次通过在多个树级上沿着码树的分支延伸路径进行解码，并且根据接收的序列计算扩展路径的可能性（度量）。 当进行到属于数据块的最后一个树级的节点时，解码被终止。 然后，将与位于具有最大度量的最后树级的节点相关联的扩展序列之一作为解码序列输出。

公开(公告)号：US4468769A

公开(公告)日：1984-08-28

申请号：US349319

申请日：1982-02-16

Applicant: Keiichiro Koga

Inventor： Keiichiro Koga

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/15

Abstract: An improved two or three error correcting system for BCH code (Bose, Chaudhuri, Hocquenghem code) has been found. In case of a two error correction system, a first syndrome A.sub.1 and a second syndrome A.sub.2 are obtained from a reception code C'=(a.sub.1 ', a.sub.2 ', . . . , a.sub.n '): ##EQU1## Then, S.sub.1 =A.sub.1 +.alpha..sup.n-t, and S.sub.2 =A.sub.2 +.alpha..sup.3(n-t) are obtained, for every value of t, where n is a code length, t is an integer equal to or less than n, and .alpha. is a primitive element of a Galois field. When A.sub.1 .noteq.0, a t'th bit a.sub.t ' is corrected by inverting the same on the condition that the t'th bit of S.sub.2 is equal to the t'th bit of S.sub.1.sup.3. When A.sub.1 =0, it is clear that no error exists, and no correction is performed. In case of a three error correction system, a third syndrome ##EQU2## and S.sub.3 =A.sub.3 +.alpha..sup.5(n-t) are obtained further for every value of t, and a correction is performed by inverting the t'th bit according to the value of EL(t)=S.sub.1.sup.6 +S.sub.2.sup.2 +S.sub.1.sup.3 S.sub.2 +S.sub.1 S.sub.3 when A.sub.1.sup.3 +A.sub.2 .noteq.0, or the value of S.sub.1 when A.sub.1.sup.3 +A.sub.2 =0. The structure of the present system is simple since said values S.sub.2, S.sub.3 and EL(t) are obtained merely by a ROM table and an exclusive-OR circuit.

Abstract translation: 已经发现了用于BCH码（Bose，Chaudhuri，Hocquenghem码）的改进的两个或三个纠错系统。 在两个纠错系统的情况下，从接收码C'=（a1'，a2'，...，an'）获得第一综合征A1和第二综合征A2：然后，S1 = A1 + 对于t的每个值，获得αnt，并且S2 = A2 +α3（nt），其中n是码长，t是等于或小于n的整数，并且α是伽罗瓦域的原始元素。 当A1 NOTEQUAL 0时，在第t个第s位等于S13的第t位的条件下，通过将其反相来校正't'的第t位。 当A1 = 0时，显然没有错误，不进行校正。 在三个错误校正系统的情况下，对于t的每个值进一步获得第三综合征和S3 = A3 +α5（nt），并且通过根据t的值反转第t位来执行校正 当A13 + A2为等于0时，EL（t）= S16 + S22 + S13S2 + S1S3，或者A13 + A2 = 0时的S1的值。 由于所述值S2，S3和EL（t）仅由ROM表和异或电路获得，所以本系统的结构是简单的。

公开(公告)号：US4320511A

公开(公告)日：1982-03-16

申请号：US129486

申请日：1980-03-11

Applicant: Keiichiro Koga ,  Yutaka Yasuda ,  Ryokichi Saga ,  Yukio Takimoto

Inventor： Keiichiro Koga ,  Yutaka Yasuda ,  Ryokichi Saga ,  Yukio Takimoto

IPC: H04L1/00 ,  G06F11/10

CPC classification number: H04L1/004

Abstract: The invention converts between a cyclic and a general code sequence, each sequence having a succession of normal code blocks and an additional or shorter code block. A zero bit series is hypothetically assumed before the additional code block. In an encoder for producing a cyclic code sequence, the zero bit series is placed before the additional code block by cooperation of a timing control circuit and a divider. In a decoder, a counter times an additional cyclic code block and starts counting while another counter is still counting to time a period, which is the period next preceding a normal cyclic code block, whereby the zero bit series is assumed.

Abstract translation: 本发明在循环代码序列和一般代码序列之间转换，每个序列具有连续的正常代码块和附加的或较短的代码块。 在附加代码块之前假设假定零位序列。 在用于产生循环码序列的编码器中，通过定时控制电路和分频器的配合，将零比特序列置于附加码块之前。 在解码器中，计数器乘以附加的循环码块并开始计数，而另一个计数器仍然计数到时间周期，即周期在正常的循环码块之前的周期，从而假设零比特序列。