公开(公告)号：US07799859B2

公开(公告)日：2010-09-21

申请号：US11629655

申请日：2005-09-09

申请人： Kazushi Kobayashi ,  Koji Beppu

发明人： Kazushi Kobayashi ,  Koji Beppu

IPC分类号： B01F17/04 ,  C08F2/24 ,  C08L71/02

CPC分类号： C08F2/24 ,  B01F17/005

摘要： A surfactant composition has good emulsifiability for monomer(s), and can provide a polymer emulsion (herein after simply called “the emulsion”) of good stability while decreasing coagulations of polymer particles in the emulsion. The surfactant composition contains the following components (A) and (B): (A) a reactive surfactant containing at least one polymerizable double-bond group and at least one ionic group in a molecule, and (B) a nitrogen compound insoluble or slightly soluble in ethanol. A weight ratio (A:B) of the component (A) to the component (B) is from 100:0.03 to 100:1.0.

摘要翻译： 表面活性剂组合物对于单体具有良好的乳化性，并且可以提供具有良好稳定性的聚合物乳液（这里简称为“乳液”），同时降低乳液中聚合物颗粒的凝结。 表面活性剂组合物含有下列组分（A）和（B）：（A）分子中含有至少一个可聚合双键基团和至少一个离子基团的反应性表面活性剂，（B）不溶于或稍微 溶于乙醇。 成分（A）与成分（B）的重量比（A:B）为100:0.03〜100:1.0。

公开(公告)号：US20090276557A1

公开(公告)日：2009-11-05

申请号：US12501684

申请日：2009-07-13

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/28

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以经由其间的数据总线传送数据，取决于t

公开(公告)号：US20050125585A1

公开(公告)日：2005-06-09

申请号：US11032051

申请日：2005-01-11

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US06841655B1

公开(公告)日：2005-01-11

申请号：US10451149

申请日：2001-12-25

申请人： Tetsuya Gota ,  Kazushi Kobayashi ,  Kaoru Komiya ,  Masahide Tsuzuki ,  Takeaki Mizutari

发明人： Tetsuya Gota ,  Kazushi Kobayashi ,  Kaoru Komiya ,  Masahide Tsuzuki ,  Takeaki Mizutari

IPC分类号： B01F17/00 ,  B01F17/18 ,  B01F17/42 ,  C08F2/24 ,  C08F2/26 ,  C08F2/28 ,  C08F220/28 ,  C08G65/34

CPC分类号： C08F2/24 ,  B01F17/0021 ,  B01F17/0028 ,  B01F17/0035 ,  B01F17/0042 ,  B01F17/005 ,  B01F17/0057 ,  B01F17/0064 ,  C08F220/28

摘要： Disclosed are surfactants represented by the following formula (1): wherein R1 represents a branched aliphatic hydrocarbon group, a secondary aliphatic hydrocarbon group or a branched aliphatic acyl group, AO and AO′ each independently represents an oxyalkylene group having 2 to 4 carbon atoms, L represents a group represented by formula (2) to be described below, z stands for a number of from 1 to 10, X represents a hydrogen atom or an ionic hydrophilic group, m stands for a number of from 0 to 1,000, and n stands for a number of from 0 to 1,000. wherein R2 and R3 each independently represents a hydrogen atom or a methyl group, x stands for a number of from 0 to 12, and y stands for a number of 0 or 1. These surfactants do not contain any phenyl ether group considered to have significant effects on the environment, such as a nonylphenyl group, and have performance comparable with reactive surfactants containing one or more phenyl ether groups. Emulsifiers for emulsion polymerization, dispersants for dispersion polymerization and resin modifiers, all of which contain the surfactants, are also disclosed.

摘要翻译： 公开了由下式（1）表示的表面活性剂：其中R 1表示支链脂族烃基，脂肪族脂族烃基或支链脂肪族酰基，AO和AO'各自独立地表示具有2〜4个碳原子的氧化烯基 碳原子，L表示由下述式（2）表示的基团，z表示1至10的数，X表示氢原子或离子性亲水基团，m表示0至1,000的数 ，n表示0〜1,000的数。R 2和R 3各自独立地表示氢原子或甲基，x表示0〜12的数，y表示 这些表面活性剂不包含被认为对环境具有显着影响的任何苯基醚基团，例如壬基苯基，并具有与含有一个或多个苯基醚基团的反应性表面活性剂相当的性能。 还公开了用于乳液聚合的乳化剂，用于分散聚合的分散剂和树脂改性剂，所有这些都包含表面活性剂。

公开(公告)号：US06810461B2

公开(公告)日：2004-10-26

申请号：US09983373

申请日：2001-10-24

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F1314

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US06330651B1

公开(公告)日：2001-12-11

申请号：US09563754

申请日：2000-05-01

申请人： Hitoshi Kawaguchi ,  Koichi Kimura ,  Hideki Kamimaki ,  Takayuki Tamura ,  Kazushi Kobayashi

发明人： Hitoshi Kawaguchi ,  Koichi Kimura ,  Hideki Kamimaki ,  Takayuki Tamura ,  Kazushi Kobayashi

IPC分类号： G06F1314

CPC分类号： G06F13/1689

摘要： An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

摘要翻译： 提供一种能够执行较高存储器访问的信息处理装置。 信息处理装置包括用于与所提供的时钟信号同步地输出数据的同步DRAM装置的存储单元，以及用于根据从CPU发出的指令来控制对存储器单元的访问的控制单元。 从控制单元输出要提供给存储单元的时钟信号。 从控制单元输出的时钟信号被提供给存储单元，并且还被拉回到控制单元。 控制单元在基于拉回时钟信号确定的定时从其中取出已经从存储单元输出的数据。 结果，控制单元减少从控制单元输出的数据的延迟与用于确定其中提取数据的定时的时钟信号的延迟之间的差异。

公开(公告)号：US5828871A

公开(公告)日：1998-10-27

申请号：US601546

申请日：1996-02-14

申请人： Hitoshi Kawaguchi ,  Koichi Kimura ,  Hideki Kamimaki ,  Takayuki Tamura ,  Kazushi Kobayashi

发明人： Hitoshi Kawaguchi ,  Koichi Kimura ,  Hideki Kamimaki ,  Takayuki Tamura ,  Kazushi Kobayashi

IPC分类号： G06F12/00 ,  G06F1/10 ,  G06F1/12 ,  G06F13/16 ,  G11C11/401 ,  G11C11/407

CPC分类号： G06F13/1689

摘要： An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

摘要翻译： 提供一种能够执行较高存储器访问的信息处理装置。 信息处理装置包括用于与所提供的时钟信号同步地输出数据的同步DRAM装置的存储单元，以及用于根据从CPU发出的指令来控制对存储器单元的访问的控制单元。 从控制单元输出要提供给存储单元的时钟信号。 从控制单元输出的时钟信号被提供给存储单元，并且还被拉回到控制单元。 控制单元在基于拉回时钟信号确定的定时从其中取出已经从存储单元输出的数据。 结果，控制单元减少从控制单元输出的数据的延迟与用于确定其中提取数据的定时的时钟信号的延迟之间的差异。

公开(公告)号：US5148539A

公开(公告)日：1992-09-15

申请号：US711254

申请日：1991-06-04

申请人： Hiromichi Enomoto ,  Kazushi Kobayashi ,  Masami Jikihara ,  Norihisa Amako

发明人： Hiromichi Enomoto ,  Kazushi Kobayashi ,  Masami Jikihara ,  Norihisa Amako

IPC分类号： G06F13/40

CPC分类号： G06F13/4018

摘要： An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units. The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit. The address bus control apparatus, when bus identifying information from a master unit identifies the memory bus, delivers first complementary address data together with address data from the master unit onto the memory bus and, when the bus identifying information identifies the system bus, delivers second complementary address data onto the system bus, and thereby secures necessary address data width for each bus.

摘要翻译： 地址总线控制装置连接与CPU和存储器单元连接的存储器总线以及与输入/输出单元连接的系统总线。 系统总线的地址总线宽度小于存储器总线的地址总线宽度，其中一个输入/输出单元是使用比用于访问另一个单元的系统总线的地址总线宽度更小的地址数据的主单元。 地址总线控制装置，当来自主单元的总线识别信息识别存储器总线时，将第一互补地址数据与来自主单元的地址数据一起传递到存储器总线上，并且当总线识别信息识别系统总线时，传送第二 补充地址数据到系统总线上，从而确保每个总线必要的地址数据宽度。

公开(公告)号：US4872131A

公开(公告)日：1989-10-03

申请号：US192547

申请日：1988-05-11

申请人： Kazumi Kubota ,  Kazushi Kobayashi ,  Toshihiko Ogura

发明人： Kazumi Kubota ,  Kazushi Kobayashi ,  Toshihiko Ogura

IPC分类号： G06F7/00 ,  G06F7/50 ,  G06F7/507 ,  G06F7/57 ,  G06F7/76

CPC分类号： G06F7/57 ,  G06F2207/3828

摘要： Two arithmetic logic units (ALUs) are provided, one a high-order side and another on a low-order side such that data on the high-order side and on low-order side, output from each of a source data register and a destination data register, are respectively supplied to the ALUs to be operated on thereby. There is provided a selector circuit on the output side of the source data register, which selector circuit operates to deliver the data on the high-order side and that on the low-order side from the source data register selectively to the ALU on the high-order side and that on the low-order side according to the operating mode. Carry outputs from each of the ALUs are input to a first selector and one is selected according to the operating mode and stored in a carry flag register. The output of the carry flag register and the carry output of the ALU on the low-order side are input to a second selector whereby one output thereof is selected according to the operating mode and input to the ALU on the high-order side as the carry input thereto, and also, the output of the carry flag register is supplied to the ALU on the low-order side as the carry input thereto.

摘要翻译： 提供两个算术逻辑单元（ALU），一个位于高阶侧，另一个位于低位侧，使得从源数据寄存器和源数据寄存器中的每一个输出的高阶侧和低位侧的数据 目的地数据寄存器分别提供给要操作的ALU。 在源数据寄存器的输出侧提供选择器电路，该选择器电路用于将高数据侧的数据和从源数据寄存器的低阶侧的数据选择性地传送到ALU的高位 - 根据操作模式在低端侧。 将来自每个ALU的输出输入到第一选择器，并根据操作模式选择一个并存储在进位标志寄存器中。 进位标志寄存器的输出和低位侧的ALU的进位输出被输入到第二选择器，由此根据操作模式选择其一个输出，并将其输入到高阶侧的ALU作为 进位输入，并且进位标志寄存器的输出也作为进位输入提供给低位侧的ALU。

公开(公告)号：US07802045B2

公开(公告)日：2010-09-21

申请号：US12501684

申请日：2009-07-13

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。