公开(公告)号：US5193196A

公开(公告)日：1993-03-09

申请号：US331297

申请日：1989-03-31

申请人： Tetsuya Mochida ,  Shigeo Tsujioka ,  Masami Jikihara ,  Hitoshi Sadamitsu ,  Kazushi Kobayashi

发明人： Tetsuya Mochida ,  Shigeo Tsujioka ,  Masami Jikihara ,  Hitoshi Sadamitsu ,  Kazushi Kobayashi

IPC分类号： G06F13/30 ,  G06F13/364

CPC分类号： G06F13/30 ,  G06F13/364

摘要： A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.

摘要翻译： 从处理单元产生的多个处理请求，例如直接存储器访问（DMA）信道由优先级电路根据分配给每个处理单元的优先级控制。 最高优先级获得的处理单元及其优先级的信息被存储在锁存器中。 禁止具有与存储的处理单元相同的优先级的另一处理请求被提供给偏好电路，使得在接受具有相同优先级的另一进程请求之前接受并执行第一生成的处理请求。

公开(公告)号：US4990907A

公开(公告)日：1991-02-05

申请号：US231000

申请日：1988-08-11

申请人： Masami Jikihara ,  Shigeo Tsujioka ,  Hiromichi Enomoto ,  Tetsuya Mochida ,  Masataka Kobayashi

发明人： Masami Jikihara ,  Shigeo Tsujioka ,  Hiromichi Enomoto ,  Tetsuya Mochida ,  Masataka Kobayashi

IPC分类号： G06F13/42

CPC分类号： G06F13/4213

摘要： A bus master and a plurality of bus slaves are connected through a data bus and a control bus, and data transfer of hand shake system is performed. In the control bus, at least data strobe signal from the bus master to the bus slave and data confirmation signal from the bus slave to the bus master are transmitted. The data strobe signal from the bus master is one inputted to a bus strobe control circuit. The data confirmation signal from the bus slave is also inputted to the bus strobe control circuit, and the control circuit supervises level of the data confirmation signal being asserted and confirms negation, and then asserts the data strobe signal to the bus slave. Thereafter, a next data transfer is started.

摘要翻译： 通过数据总线和控制总线连接总线主机和多个总线从机，执行手抖动系统的数据传送。 在控制总线中，至少从总线主机到总线从站的数据选通信号和从总线从站到总线主站的数据确认信号。 来自总线主机的数据选通信号是输入到总线选通控制电路的信号。 来自总线从站的数据确认信号也被输入到总线选通控制电路，控制电路对数据确认信号的电平进行监控，并确认为否定，然后将数据选通信号置为总线从站。 此后，开始下一次数据传送。

公开(公告)号：US5276818A

公开(公告)日：1994-01-04

申请号：US512810

申请日：1990-04-20

申请人： Koichi Okazawa ,  Hiroaki Aotsu ,  Hitoshi Kawaguchi ,  Masami Jikihara ,  Kazushi Kobayashi ,  Koichi Kimura ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Hiroaki Aotsu ,  Hitoshi Kawaguchi ,  Masami Jikihara ,  Kazushi Kobayashi ,  Koichi Kimura ,  Tetsuya Mochida

IPC分类号： G06F13/28 ,  G06F13/36 ,  G06F13/364 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4217 ,  G06F13/364

摘要： A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.

摘要翻译： 一种用于信息处理系统的总线系统，其中在公共总线上控制多个模块之间的数据传输。 响应于来自模块的总线使用请求，发出用于中止由具有较低优先级的另一模块执行的数据传输的命令。 正在传送数据的模块通过发出一个指示要传送的字是最终字的信号来响应中止命令。 通过与从总线控制器提供的时钟同步的与数据具有相同宽度的地址总线，在主机和从机之间传送数据。

公开(公告)号：US5148539A

公开(公告)日：1992-09-15

申请号：US711254

申请日：1991-06-04

申请人： Hiromichi Enomoto ,  Kazushi Kobayashi ,  Masami Jikihara ,  Norihisa Amako

发明人： Hiromichi Enomoto ,  Kazushi Kobayashi ,  Masami Jikihara ,  Norihisa Amako

IPC分类号： G06F13/40

CPC分类号： G06F13/4018

摘要： An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units. The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit. The address bus control apparatus, when bus identifying information from a master unit identifies the memory bus, delivers first complementary address data together with address data from the master unit onto the memory bus and, when the bus identifying information identifies the system bus, delivers second complementary address data onto the system bus, and thereby secures necessary address data width for each bus.

摘要翻译： 地址总线控制装置连接与CPU和存储器单元连接的存储器总线以及与输入/输出单元连接的系统总线。 系统总线的地址总线宽度小于存储器总线的地址总线宽度，其中一个输入/输出单元是使用比用于访问另一个单元的系统总线的地址总线宽度更小的地址数据的主单元。 地址总线控制装置，当来自主单元的总线识别信息识别存储器总线时，将第一互补地址数据与来自主单元的地址数据一起传递到存储器总线上，并且当总线识别信息识别系统总线时，传送第二 补充地址数据到系统总线上，从而确保每个总线必要的地址数据宽度。