公开(公告)号：US07834601B2

公开(公告)日：2010-11-16

申请号：US11937959

申请日：2007-11-09

申请人： Masami Aiura ,  Kanji Egawa ,  Shintaroh Murakami

发明人： Masami Aiura ,  Kanji Egawa ,  Shintaroh Murakami

IPC分类号： G05F1/40 ,  H02M7/10

CPC分类号： H02M3/156 ,  H02M2001/0022 ,  Y10S323/901

摘要： A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

摘要翻译： 一种在开始脉宽调制模式时降低输出噪声的电路和方法。 脉冲宽度调制电路产生具有与调节器电路的输出电压相应的占空比的第一脉冲信号。 驱动电路响应于从脉宽调制电路提供的第一脉冲信号，从输入电压产生输出电压。 前馈电路以脉冲宽度调制电路向驱动电路提供第一脉冲信号的方式控制脉宽调制电路，以产生具有将输出电压保持在期望电平的占空比的第一脉冲信号。

公开(公告)号：US6081146A

公开(公告)日：2000-06-27

申请号：US936117

申请日：1997-09-24

申请人： Masuzumi Shiochi ,  Kanji Egawa

发明人： Masuzumi Shiochi ,  Kanji Egawa

IPC分类号： G06F1/10 ,  H03K5/00 ,  H03K5/135 ,  H03L7/081 ,  H03H11/26

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03K5/135 ,  H03L7/0812 ,  H03K2005/00032 ,  H03K2005/00104

摘要： An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal. A phase difference detection circuit receives an output signal of a flip-flop provided on an output end of a data line of the integrated circuit and an output signal of the phase difference compensation circuit, detects phase difference between both output signals and outputs the control signal in response to the phase difference.

摘要翻译： 接口单元发送具有对应于延迟时间控制信号的延迟时间的信号。 延迟时间控制电路由延迟链和PLL电路组成。 延迟链包括多个串联连接的接口单元，提供给提供时钟信号的头单元，然后在任意阶段从接口单元获取时钟信号的延迟信号。 PLL电路产生延迟时间控制信号，以使时钟信号和延迟信号之间的相位相等。 这是一个延迟单元。 在集成电路的时钟线的输出端提供相位差补偿电路，以便基于输入控制信号延迟输入时钟信号。 相位差检测电路接收设置在集成电路的数据线的输出端的触发器的输出信号和相位差补偿电路的输出信号，检测两个输出信号之间的相位差，并输出控制信号 响应于相位差。

公开(公告)号：US20100187526A1

公开(公告)日：2010-07-29

申请号：US12613543

申请日：2009-11-06

申请人： Kanji Egawa ,  Akihiro Zemba

发明人： Kanji Egawa ,  Akihiro Zemba

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device semiconductor device allowing for use of a test circuit that withstands only low voltages and has a small circuit area. A high-voltage operational circuit, which is operated at a high voltage, is connected to first and second pads. A multiplexer used to test the high-voltage operational circuit is connected to a third pad in addition to the first and second pads. Fuses are arranged on wires connecting the first and second pads to the multiplexer. An inspection board connects the third pad to ground after testing the high-voltage operational circuit, provides a breakage signal to the multiplexer, and applies voltage to the first or second pad. The multiplexer, which receives the breakage signal, connects the first or second pad with the third pad so that current flows therebetween. This breaks the corresponding fuse and insulates the multiplexer from the high-voltage operational circuit.

摘要翻译： 一种半导体器件半导体器件，其允许使用仅承受低电压且电路面积小的测试电路。 在高电压下工作的高电压操作电路连接到第一和第二焊盘。 用于测试高电压操作电路的多路复用器除了第一和第二焊盘之外还连接到第三焊盘。 保险丝布置在将第一和第二焊盘连接到复用器的电线上。 检测板在测试高电压操作电路之后将第三焊盘连接到地，向多路复用器提供断线信号，并向第一或第二焊盘施加电压。 接收断裂信号的多路复用器将第一或第二焊盘与第三焊盘连接，使得电流在其间流动。 这会破坏相应的保险丝，并将多路复用器与高压运行电路绝缘。

公开(公告)号：US07692464B2

公开(公告)日：2010-04-06

申请号：US12050172

申请日：2008-03-18

申请人： Shintaroh Murakami ,  Kanji Egawa

发明人： Shintaroh Murakami ,  Kanji Egawa

IPC分类号： H03K3/017

CPC分类号： H03K7/08

摘要： A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.

摘要翻译： 有效且准确地输出双PWM波的脉冲宽度调制（PWM）波形输出电路包括两个比较器，OR电路和AND电路。 电压发生器为比较器提供具有相同波高和相移相位的斜坡电压。 比较器将斜坡电压与参考电压进行比较，并将比较结果提供给OR电路和AND电路。 OR电路输出第一调制波，AND电路产生第二调制波。 因此，基于具有不同相位的斜坡电压输出具有不同占空比的调制波。

公开(公告)号：US20080246523A1

公开(公告)日：2008-10-09

申请号：US12050172

申请日：2008-03-18

申请人： Shintaroh MURAKAMI ,  Kanji Egawa

发明人： Shintaroh MURAKAMI ,  Kanji Egawa

IPC分类号： H03K3/017

CPC分类号： H03K7/08

摘要： A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.

摘要翻译： 有效且准确地输出双PWM波的脉冲宽度调制（PWM）波形输出电路包括两个比较器，OR电路和AND电路。 电压发生器为比较器提供具有相同波高和相移相位的斜坡电压。 比较器将斜坡电压与参考电压进行比较，并将比较结果提供给OR电路和AND电路。 OR电路输出第一调制波，AND电路产生第二调制波。 因此，基于具有不同相位的斜坡电压输出具有不同占空比的调制波。

公开(公告)号：US06275115B1

公开(公告)日：2001-08-14

申请号：US09515324

申请日：2000-02-29

申请人： Kanji Egawa

发明人： Kanji Egawa

IPC分类号： H03L7085

CPC分类号： H03L7/187 ,  H03L7/099 ,  H03L7/10

摘要： A PLL circuit includes: a phase comparator for comparing the phase of an input signal with the phase of a reference input signal to output a signal according to the phase difference therebetween; a low pass filter for outputting a low frequency control voltage on the basis of the output of the phase comparator; a voltage control oscillator for controlling an oscillating frequency on the basis of the control voltage; and a characteristic control part for controlling the characteristic of oscillating frequency to control voltage of the voltage control oscillator on the basis of n+1 ranges of first through n+1-th ranges obtained by dividing a variable range of the control voltage by first through n-th (n≧2) thresholds which are different from each other. Thus, it is possible to widen the operating frequency range, and it is possible to inhibit the frequency variation due to noises.

摘要翻译： PLL电路包括：相位比较器，用于将输入信号的相位与参考输入信号的相位进行比较，以根据它们之间的相位差输出信号; 低通滤波器，用于根据相位比较器的输出输出低频控制电压; 用于基于所述控制电压来控制振荡频率的电压控制振荡器; 以及特征控制部分，用于基于通过将控制电压的可变范围除以第一到第n至第1到第n + 1个范围的n + 1范围来控制振荡频率的特性来控制压控振荡器的电压 第n（n> = 2）个阈值彼此不同。 因此，可以扩大工作频率范围，并且可以抑制由于噪声引起的频率变化。

公开(公告)号：US20100194362A1

公开(公告)日：2010-08-05

申请号：US12617732

申请日：2009-11-13

申请人： Kanji EGAWA

发明人： Kanji EGAWA

IPC分类号： G05F1/10

CPC分类号： H02M3/156

摘要： A pulse width modulation circuit that controls the output voltage of a regulator. The regulator includes a switching element, which is activated and deactivated by a pulse signal, and a PMW control circuit, which provides the switching element with the pulse signal in accordance with a duty ratio determined from a reference voltage and an error voltage. The error voltage is the difference between the output voltage and reference voltage. The PWM control circuit includes a current source that generates a current in accordance with the error voltage, a capacitor arranged between the current source and ground, and a comparator. The comparator has a non-inverting input terminal, which is connected between the current source and capacitor, and an inverting input terminal, to which the reference voltage is applied. An output signal of the comparator is provided to the switching element.

摘要翻译： 用于控制调节器的输出电压的脉宽调制电路。 调节器包括通过脉冲信号激活和去激活的开关元件和PMW控制电路，其根据从参考电压和误差电压确定的占空比向开关元件提供脉冲信号。 误差电压是输出电压和参考电压之间的差值。 PWM控制电路包括根据误差电压产生电流的电流源，布置在电流源和地之间的电容器和比较器。 比较器具有连接在电流源和电容器之间的非反相输入端子和施加参考电压的反相输入端子。 比较器的输出信号被提供给开关元件。

公开(公告)号：US20100045250A1

公开(公告)日：2010-02-25

申请号：US12198099

申请日：2008-08-25

申请人： Masami AIURA ,  Kanji Egawa

发明人： Masami AIURA ,  Kanji Egawa

IPC分类号： G05F1/00

CPC分类号： H02M1/32 ,  H02M3/1588 ,  Y02B70/1466

摘要： A method and circuit for accurately detecting an output short circuit in a switching regulator. A first transistor and a second transistor are connected in series and driven in a complementary manner. A comparator compares output current, which is generated when the first and second transistors are driven, with a short circuit detection threshold to generate a first short circuit detection signal. A timing controller retrieves the first short circuit detection signal generated by the comparator at a predetermined time to generate a second short circuit detection signal.

摘要翻译： 一种用于精确检测开关调节器中的输出短路的方法和电路。 第一晶体管和第二晶体管串联连接并以互补方式驱动。 比较器比较驱动第一和第二晶体管时产生的输出电流与短路检测阈值，以产生第一短路检测信号。 定时控制器在预定时间检索由比较器产生的第一短路检测信号，以产生第二短路检测信号。

公开(公告)号：US20090121697A1

公开(公告)日：2009-05-14

申请号：US11937959

申请日：2007-11-09

申请人： Masami Aiura ,  Kanji Egawa ,  Shintaroh Murakami

发明人： Masami Aiura ,  Kanji Egawa ,  Shintaroh Murakami

IPC分类号： G05F1/10 ,  G05F1/02

CPC分类号： H02M3/156 ,  H02M2001/0022 ,  Y10S323/901

摘要： A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

摘要翻译： 一种在开始脉宽调制模式时降低输出噪声的电路和方法。 脉冲宽度调制电路产生具有与调节器电路的输出电压相应的占空比的第一脉冲信号。 驱动电路响应于从脉宽调制电路提供的第一脉冲信号，从输入电压产生输出电压。 前馈电路以脉冲宽度调制电路向驱动电路提供第一脉冲信号的方式控制脉宽调制电路，以产生具有将输出电压保持在期望电平的占空比的第一脉冲信号。

公开(公告)号：US06294944B1

公开(公告)日：2001-09-25

申请号：US09494032

申请日：2000-01-31

申请人： Masuzumi Shiochi ,  Kanji Egawa

发明人： Masuzumi Shiochi ,  Kanji Egawa

IPC分类号： H03L500

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03K5/135 ,  H03K2005/00032 ,  H03K2005/00104 ,  H03L7/0812

摘要： An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal. A phase difference detection circuit receives an output signal of a flip-flop provided on an output end of a data line of the integrated circuit and an output signal of the phase difference compensation circuit, detects phase difference between both output signals and outputs the control signal in response to the phase difference.

摘要翻译： 接口单元发送具有对应于延迟时间控制信号的延迟时间的信号。 延迟时间控制电路由延迟链和PLL电路组成。 延迟链包括多个串联连接的接口单元，提供给提供时钟信号的头单元，然后在任意阶段从接口单元获取时钟信号的延迟信号。 PLL电路产生延迟时间控制信号，以使时钟信号和延迟信号之间的相位相等。 这是一个延迟单元。 在集成电路的时钟线的输出端提供相位差补偿电路，以便基于输入控制信号延迟输入时钟信号。 相位差检测电路接收设置在集成电路的数据线的输出端的触发器的输出信号和相位差补偿电路的输出信号，检测两个输出信号之间的相位差，并输出控制信号 响应于相位差。