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公开(公告)号：US12086620B2
公开(公告)日：2024-09-10
申请号：US17142946
申请日：2021-01-06
发明人： Zhibiao Zhao , Yueqiang Cheng
CPC分类号： G06F9/45558 , G06F9/44505 , G06F9/4856 , G06F2009/4557 , G06F2009/45591 , G06F2009/45595
摘要： Systems and methods are disclosed for migrating a virtual machine (VM) having a virtual function that maps resources of an artificial intelligence (AI) accelerator to the VM. A driver for the AI accelerator can generate a checkpoint of VM processes that make calls to the AI accelerator, and can the checkpoint can include a list and configuration of resources mapped to the AI accelerator by the virtual function. The driver can also access the code, data, and memory of the AI accelerator to generate a checkpoint of the AI accelerator status. When the VM is migrated to a new host, then either, or both, of these checkpoint frames can be used to ensure that resuming the VM on a new host having appropriate AI accelerator resources, can be successful resumed on the new host. One or both checkpoint frames can be captured based upon an event, in anticipation of the need to migrate the VM.
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公开(公告)号：US12072780B2
公开(公告)日：2024-08-27
申请号：US17808282
申请日：2022-06-22
发明人： Zhao Zhang
IPC分类号： G06F11/273 , G06F11/22 , G06F11/34 , G06F18/214
CPC分类号： G06F11/2733 , G06F11/2236 , G06F11/2273 , G06F11/3409 , G06F18/214
摘要： Provided are a method and an apparatus for testing AI chip computing performance, and a non-transitory computer-readable storage medium. The method includes: forming computing performance result data of a to-be-tested AI chip according to a plurality of items of simulation data formed in a development process of the to-be-tested AI chip; acquiring a function instruction set matched with a to-be-tested service function, wherein the function instruction set is composed of a plurality of instructions in a standard instruction set matched with the to-be-tested AI chip; and predicting computing time required by the to-be-tested AI chip to execute the to-be-tested service function according to the function instruction set and the computing performance result data.
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公开(公告)号：US20240126610A1
公开(公告)日：2024-04-18
申请号：US18520646
申请日：2023-11-28
发明人： Runze LI , Shiyu ZHU , Baoyu ZHOU
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/5016 , G06F9/5044
摘要： An apparatus and a method of processing data, an electronic device, and a storage medium are provided, which relate to a field of artificial intelligence, and in particular to fields of chip and multi-thread parallel technologies. The apparatus includes: a first target storage unit; and a processor configured to: determine an initial number of threads according to a data amount of target data and a capacity of the first target storage unit in response to determining that the data amount is less than or equal to the capacity of the first target storage unit, where the target data includes input data to be processed, weight data to be processed, and output data; and determine a first number of executable tasks according to the initial number of threads in response to determining that the initial number of threads is greater than or equal to a predetermined number of threads.
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4.发明授权公开(公告)号：US11748108B2
公开(公告)日：2023-09-05
申请号：US17210616
申请日：2021-03-24
申请人： Beijing Baidu Netcom Science and Technology Co., Ltd. , Kunlunxin Technology (Beijing) Company Limited
发明人： Yingnan Xu , Jian Ouyang , Xueliang Du , Kang An
CPC分类号： G06F9/3834 , G06F9/30087 , G06F9/3838
摘要： Example embodiments of the present application provide an instruction executing method and apparatus, an electronic device, and a computer-readable storage medium that may be applied in the field of artificial intelligence. The instruction executing method may include: executing an instruction sequence that includes memory instructions and non-memory instructions, the instructions in the sequence executed starting to be executed in order; determining that execution of a first memory instruction needs to be completed before a second memory instruction starts to be executed, the second memory instruction being a next memory instruction following the first memory instruction in the instruction sequence; and executing non-memory instructions between the first memory instruction and the second memory instruction without executing the second memory instruction, during a cycle of executing the first memory instruction.
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公开(公告)号：US11609766B2
公开(公告)日：2023-03-21
申请号：US16315890
申请日：2019-01-04
申请人： Baidu USA LLC , Baidu.com Times Technology (Beijing) Co., Ltd. , KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
发明人： Yueqiang Cheng , Yong Liu , Tao Wei , Jian Ouyang
IPC分类号： G06F9/4401 , G06F9/30 , G06F9/38 , G06F9/54
摘要： According to one embodiment, a data processing system performs a secure boot using a security module (e.g., a trusted platform module (TPM)) of a host system. The system verifies that an operating system (OS) and one or more drivers including an accelerator driver associated with a data processing (DP) accelerator is provided by a trusted source. The system launches the accelerator driver within the OS. The system generates a trusted execution environment (TEE) associated with one or more processors of the host system. The system launches an application and a runtime library within the TEE, where the application communicates with the DP accelerator via the runtime library and the accelerator driver.
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公开(公告)号：US11422817B2
公开(公告)日：2022-08-23
申请号：US16458381
申请日：2019-07-01
发明人： Jing Wang , Wei Qi , Yupeng Li , Xiaozhang Gong
IPC分类号： G06F9/38
摘要： A method and apparatus for executing an instruction are provided. In the method, an instruction queue is first generated, and an instruction from the instruction queue in preset order is acquired. Then, a sending step including: determining a type of the acquired instruction; determining, in response to determining that the acquired instruction is an arithmetic instruction, an executing component for executing the arithmetic instruction from an executing component set; and sending the arithmetic instruction to the determined executing component is executed. Last, in response to determining that the acquired instruction is a blocking instruction, a next instruction is acquired after receiving a signal for instructing an instruction associated with the blocking instruction being completely executed.
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公开(公告)号：US12032980B2
公开(公告)日：2024-07-09
申请号：US16891508
申请日：2020-06-03
发明人： Yueqiang Cheng , Zhibiao Zhao
CPC分类号： G06F9/45558 , G06F9/5011 , G06F2009/45583
摘要： Embodiments of the disclosure discloses a method and system of a virtualization environment for a data processing (DP) accelerator. In one embodiment, a data processing (DP) accelerator includes a resource management unit and one or more dynamically isolated resources managed by the resource management unit. The DP accelerator includes one or more virtual functions (VFs) each associated with one of the one or more dynamically isolated resources, where a virtual machine (VM) of a host is assigned one of the one or more VFs to access the dynamically isolated resources associated with the assigned VF, and where the VM has no access to the rest of the one or more dynamically isolated resources.
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公开(公告)号：US11847501B2
公开(公告)日：2023-12-19
申请号：US16899852
申请日：2020-06-12
发明人： Yueqiang Cheng , Hefei Zhu
CPC分类号： G06F9/5061 , G06F9/468 , G06F9/5016 , G06F9/5027 , G06F21/602
摘要： Systems and methods are disclosed for data protection in a cluster of data processing accelerators (DPAs) using a policy that determines a static partition of resources in each DPA in the cluster communicatively coupled to a host device. Each DPA has sensitive (secure) and non-sensitive (non-secure) resources. The host device and a DPA can access all resources of the DPA. Other DPAs can only access non-sensitive resources of a DPA. The partition of resources within a DPA is static and may be implemented in hardware or firmware. Resources include memory, one or more processing modules such as key generators and cryptographic modules, caches, registers, and storage.
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公开(公告)号：US11782722B2
公开(公告)日：2023-10-10
申请号：US17149476
申请日：2021-01-14
申请人： BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD. , KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
发明人： Baofu Zhao , Xueliang Du , Kang An , Yingnan Xu , Chao Tang
IPC分类号： G06F9/38
CPC分类号： G06F9/3877 , G06F9/3836
摘要： A complex computing device, a complex computing method, an artificial intelligence chip and an electronic apparatus are provided. An input interface receives complex computing instructions and arbitrates each complex computing instruction to a corresponding computing component respectively, according to the computing types in the respective complex computing instructions Each computing component is connected to the input interface, acquires a source operand from a complex computing instruction to perform complex computing, and generates a computing result instruction to feed back to an output interface. The output interface arbitrates the computing result in each computing result instruction to the corresponding instruction source respectively, according to the instruction source identifier in each computing result instruction.
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公开(公告)号：US11775347B2
公开(公告)日：2023-10-03
申请号：US16598129
申请日：2019-10-10
发明人： Yueqiang Cheng , Yong Liu
CPC分类号： G06F9/5027 , G06F21/16 , G06N5/04 , G06N20/10
摘要： In one embodiment, a computer-implemented method performed by a data processing (DP) accelerator includes receiving, at the DP accelerator, first data representing an artificial intelligence (AI) model that has been previously trained from a host processor; receiving, at the DP accelerator, a request to implant a watermark in the AI model from the host processor; and implanting, by the DP accelerator, the watermark within the AI model. The DP accelerator then transmits second data representing the AI model having the watermark implanted therein to the host processor. In embodiment, the method further includes extracting, at the DP accelerator, a watermark algorithm identifier (ID) from the request to implant a watermark; and generating the watermark using a watermark algorithm identified by the watermark algorithm ID.
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