公开(公告)号：US20170104068A1

公开(公告)日：2017-04-13

申请号：US15251510

申请日：2016-08-30

申请人： DONG-SIK LEE ,  YOUNGWOO KIM ,  JINHYUN SHIN ,  JUNG HOON LEE

发明人： DONG-SIK LEE ,  YOUNGWOO KIM ,  JINHYUN SHIN ,  JUNG HOON LEE

IPC分类号： H01L29/10 ,  G11C16/08 ,  H01L23/528 ,  H01L29/423 ,  H01L27/115 ,  H01L23/522

CPC分类号： H01L27/11551 ,  H01L21/26506 ,  H01L21/28158 ,  H01L21/823462 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11246 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/1083 ,  H01L29/42368

摘要： A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

公开(公告)号：US20110062508A1

公开(公告)日：2011-03-17

申请号：US12882436

申请日：2010-09-15

申请人： Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

发明人： Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

IPC分类号： H01L29/788

CPC分类号： H01L27/11531 ,  H01L27/11526 ,  H01L28/20 ,  H01L28/24

摘要： Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

摘要翻译： 提供了包括电阻器的半导体器件及其制造方法的实施例。 半导体器件包括设置在半导体衬底上以限定沟槽的模具图案，包括主体区域和第一和第二接触区域的电阻图案，其中主体区域覆盖沟槽的底部和侧壁，第一和第二接触区域 分别从模具图案的上表面上的身体区域延伸出来; 以及分别与第一和第二接触区域接触的第一和第二线路。

公开(公告)号：US20170243886A1

公开(公告)日：2017-08-24

申请号：US15592030

申请日：2017-05-10

申请人： Jung Hoon LEE ,  Keejeong RHO ,  Sejun PARK ,  Jinhyun SHIN ,  Dong-Sik LEE ,  Woong-Seop LEE

发明人： Jung Hoon LEE ,  Keejeong RHO ,  Sejun PARK ,  Jinhyun SHIN ,  Dong-Sik LEE ,  Woong-Seop LEE

IPC分类号： H01L27/11582 ,  G11C16/08 ,  H01L23/528

CPC分类号： H01L27/11582 ,  G11C16/08 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157

摘要： A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

公开(公告)号：US20130187233A1

公开(公告)日：2013-07-25

申请号：US13584193

申请日：2012-08-13

申请人： Jaesun YUN ,  Jeongseok NAM ,  Jinhyun SHIN

发明人： Jaesun YUN ,  Jeongseok NAM ,  Jinhyun SHIN

IPC分类号： H01L27/105

CPC分类号： H01L27/11524 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device may include: a well impurity layer including a cell array region and a well drive region adjacent to the cell array region, the well impurity layer having a first conductivity type; at least one word line on the well impurity layer; at least one bit line crossing the at least one word line on the well impurity layer of the cell array region, the at least one bit line connected to a drain region in the well impurity layer, and the drain region having a second conductivity type; and a well drive line crossing the at least one word line on the well impurity layer of the well drive region, the well drive line connected to the well impurity layer of the first conductivity type.

摘要翻译： 半导体存储器件可以包括：阱杂质层，其包括与电池阵列区域相邻的电池阵列区域和阱驱动区域，阱杂质层具有第一导电类型; 井杂质层上至少有一条字线; 与单元阵列区的阱杂质层上的至少一个字线交叉的至少一个位线，连接到阱杂质层中的漏极区的至少一个位线，以及具有第二导电类型的漏极区; 以及与阱驱动区域的阱杂质层上的至少一条字线交叉的阱驱动线，阱驱动线连接到第一导电类型的阱杂质层。

公开(公告)号：US08154104B2

公开(公告)日：2012-04-10

申请号：US12077379

申请日：2008-03-19

申请人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

发明人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

IPC分类号： H01L27/06

CPC分类号： H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括包括第一区域和第二区域的衬底。 至少一个第一栅极结构在第一区域中的衬底上，所述至少一个第一栅极结构包括第一栅极绝缘层和第一栅极绝缘层上的第一栅极电极层。 至少一个隔离结构位于第二区域中的衬底中，隔离结构的顶表面的高度低于衬底的顶表面。 至少一个隔离结构上至少有一个电阻器图案。

公开(公告)号：US20090051008A1

公开(公告)日：2009-02-26

申请号：US12077379

申请日：2008-03-19

申请人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

发明人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括包括第一区域和第二区域的衬底。 至少一个第一栅极结构在第一区域中的衬底上，所述至少一个第一栅极结构包括第一栅极绝缘层和第一栅极绝缘层上的第一栅极电极层。 至少一个隔离结构位于第二区域中的衬底中，隔离结构的顶表面的高度低于衬底的顶表面。 至少一个隔离结构上至少有一个电阻器图案。

公开(公告)号：US20140151777A1

公开(公告)日：2014-06-05

申请号：US14096195

申请日：2013-12-04

申请人： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

发明人： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L21/764 ,  H01L29/42324

摘要： Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

摘要翻译： 提供一种半导体存储器件及其制造方法，半导体存储器件可以包括半导体衬底，该半导体衬底具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，栅极 电极，设置在第一区域上以与有源区交叉，设置在栅电极和有源区之间的电荷存储图案，设置在栅电极和电荷存储图案之间并在第一沟槽上延伸以限定第一 第一沟槽中的空气间隙，以及设置成与第二沟槽的底表面间隔开的绝缘图案，以在第二沟槽中限定第二气隙。

公开(公告)号：US20140080278A1

公开(公告)日：2014-03-20

申请号：US14089075

申请日：2013-11-25

申请人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Chol

发明人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Chol

IPC分类号： H01L27/105

CPC分类号： H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括包括第一区域和第二区域的衬底。 至少一个第一栅极结构在第一区域中的衬底上，所述至少一个第一栅极结构包括第一栅极绝缘层和第一栅极绝缘层上的第一栅极电极层。 至少一个隔离结构位于第二区域中的衬底中，隔离结构的顶表面的高度低于衬底的顶表面。 至少一个隔离结构上至少有一个电阻器图案。

公开(公告)号：US08610218B2

公开(公告)日：2013-12-17

申请号：US13412700

申请日：2012-03-06

申请人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

发明人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

IPC分类号： H01L27/06

CPC分类号： H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括包括第一区域和第二区域的衬底。 至少一个第一栅极结构在第一区域中的衬底上，所述至少一个第一栅极结构包括第一栅极绝缘层和第一栅极绝缘层上的第一栅极电极层。 至少一个隔离结构位于第二区域中的衬底中，隔离结构的顶表面的高度低于衬底的顶表面。 至少一个隔离结构上至少有一个电阻器图案。

公开(公告)号：US20120168871A1

公开(公告)日：2012-07-05

申请号：US13412700

申请日：2012-03-06

申请人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

发明人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

IPC分类号： H01L27/06

CPC分类号： H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括包括第一区域和第二区域的衬底。 至少一个第一栅极结构在第一区域中的衬底上，所述至少一个第一栅极结构包括第一栅极绝缘层和第一栅极绝缘层上的第一栅极电极层。 至少一个隔离结构位于第二区域中的衬底中，隔离结构的顶表面的高度低于衬底的顶表面。 至少一个隔离结构上至少有一个电阻器图案。