公开(公告)号：US08468286B2

公开(公告)日：2013-06-18

申请号：US13007332

申请日：2011-01-14

申请人： Cong Yao ,  Qiwei Liu ,  Yu Liu ,  Xiang Li ,  Liqian Chen ,  Shiming He ,  Jiayin Lu

发明人： Cong Yao ,  Qiwei Liu ,  Yu Liu ,  Xiang Li ,  Liqian Chen ,  Shiming He ,  Jiayin Lu

IPC分类号： G06F5/06

CPC分类号： G06F13/382

摘要： A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).

摘要翻译： 提供了可变频率总线适配器，可变频率总线适配方法和可变频率总线适配系统。 该方法包括：根据由总线端发送的动态频率缩放（DFS）请求信号产生总线阻塞指示; 根据总线阻塞指示阻止当前总线传输; 并且在阻止当前总线传输之后将DFS响应信号反馈给总线侧，其中DFS响应信号适于使总线端执行DFS操作。 在该方法中，在DFS期间暂时阻塞总线传输，从而在不增加系统的时钟域数量或修改外围组件的情况下减少总线DFS期间由不稳定总线块引起的对外围组件的不良影响，从而减少 实现系统的复杂性，并提高动态电压频率缩放（DVFS）的适用性。

公开(公告)号：US08204218B2

公开(公告)日：2012-06-19

申请号：US12375095

申请日：2007-07-19

申请人： Jiayin Lu ,  Jun Cao ,  Zhenhai Huang ,  Xiang Yan

发明人： Jiayin Lu ,  Jun Cao ,  Zhenhai Huang ,  Xiang Yan

IPC分类号： H04K1/00

CPC分类号： H04L9/0625 ,  H04L2209/80

摘要： An encrypting/decrypting processing method for implementing SMS4 algorithm in high efficiency is provided. After preparing constant array, input external data into register section, firstly make primary data conversion and then make secondary data conversion, finally repeat data conversion course until complete all specified data conversion courses and obtain processing result of circulating data encryption/decryption. And it solves the technical problems of data conversion in the background technique that number of circulating times is large and encrypting efficiency is low, simplifying the chip design, largely optimizing integrity of chip signal and being able to improve interference immunity of system and reduce system cost.

摘要翻译： 提供了一种以高效率实现SMS4算法的加密/解密处理方法。 准备常数阵列后，将外部数据输入到寄存器部分，首先进行主数据转换，然后进行二次数据转换，最后重复数据转换过程，直到完成所有指定的数据转换课程，并获得循环数据加密/解密的处理结果。 解决了循环次数大，加密效率低的背景技术数据转换技术问题，简化了芯片设计，大大提高了芯片信号的完整性，提高了系统的抗干扰能力，降低了系统成本 。

公开(公告)号：US20100241885A1

公开(公告)日：2010-09-23

申请号：US12725281

申请日：2010-03-16

申请人： Shiming He ,  Yu Liu ,  Cong Yao ,  Xiang Li ,  Liqian Chen ,  Jiayin Lu

发明人： Shiming He ,  Yu Liu ,  Cong Yao ,  Xiang Li ,  Liqian Chen ,  Jiayin Lu

IPC分类号： G06F1/30 ,  G06F13/24

CPC分类号： G06F1/3203 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Embodiments of the present disclosure disclose a method for controlling power consumption of an embedded system. The method obtains a data transmission index that is between a bus module and a bus, compares the obtained data transmission index with a preset numeric value range, and adjusts an operation frequency or an operation voltage of the bus module when the data transmission index exceeds the preset numeric value range. Embodiments of the present disclosure further provide a system and a relevant apparatus for controlling power consumption of the embedded system. In comparison with the conventional art, embodiments of the present disclosure effectively monitor the load of the bus module, and adjust the operation parameters of the module according to the monitoring result to enable the module to operate under proper operation parameters and to thereby reduce unnecessary power consumption.

摘要翻译： 本公开的实施例公开了一种用于控制嵌入式系统的功耗的方法。 该方法获得总线模块和总线之间的数据传输索引，将获得的数据传输指数与预设数值范围进行比较，并且当数据传输指数超过总线模块时调整总线模块的工作频率或工作电压 预设数值范围。 本公开的实施例还提供了一种用于控制嵌入式系统的功耗的系统和相关装置。 与传统技术相比，本公开的实施例有效地监视总线模块的负载，并且根据监视结果调整模块的操作参数，以使模块能够在适当的操作参数下操作，从而减少不必要的功率 消费。

公开(公告)号：US08605893B2

公开(公告)日：2013-12-10

申请号：US13465411

申请日：2012-05-07

申请人： Jiayin Lu ,  Jun Cao ,  Xiang Yan ,  Zhenhai Huang

发明人： Jiayin Lu ,  Jun Cao ,  Xiang Yan ,  Zhenhai Huang

IPC分类号： H04K1/00

CPC分类号： G09C1/00 ,  H04L9/0625 ,  H04L9/14 ,  H04L2209/125

摘要： An encryption and decryption processing system for achieving SMS4 cryptographic procedure can be provided. The system includes a repeating encryption and decryption data processing device comprising a first constant array storing unit, a first data registering unit and a first data converting unit. The first constant array storing unit stores a first constant array and send it to N-data converting sub-units of the first data converting unit. The first data registering unit registers data, deliver the registered data to a first data converting sub-unit. The N-data converting sub-units perform a data conversion processing, and transmit the obtained conversion data to a next data converting sub-unit for subsequent processing until the data conversion processing processes are completed, a particular number of the completed processed being equal to a value of a data depth.

摘要翻译： 可以提供用于实现SMS4密码过程的加密和解密处理系统。 该系统包括重复的加密和解密数据处理装置，包括第一常数阵列存储单元，第一数据登记单元和第一数据转换单元。 第一常数阵列存储单元存储第一常数阵列并将其发送到第一数据转换单元的N数据转换子单元。 第一数据登记单元登记数据，将注册的数据传送到第一数据转换子单元。 N数据转换子单元执行数据转换处理，并将所获得的转换数据发送到下一个数据转换子单元，用于后续处理，直到数据转换处理完成，完成处理的特定数量等于 数据深度的值。

公开(公告)号：US08570087B2

公开(公告)日：2013-10-29

申请号：US13311069

申请日：2011-12-05

申请人： Shiming He ,  Liqian Chen ,  Cong Yao ,  Xiang Li ,  Yu Liu ,  Jiayin Lu

发明人： Shiming He ,  Liqian Chen ,  Cong Yao ,  Xiang Li ,  Yu Liu ,  Jiayin Lu

IPC分类号： H03K3/00

CPC分类号： H03L7/0997

摘要： The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.

摘要翻译： 本发明提供一种提供时钟信号的时钟电路和方法。 时钟电路包括：自适应时钟产生电路，被配置为输出自适应时钟信号; 以及自适应时钟驱动电路，被配置为由自适应时钟信号驱动工作。 自适应时钟驱动电路的最大可工作频率高于或等于自适应时钟信号的频率。 当自适应时钟驱动电路的工作状态改变时，自适应时钟驱动电路的最大可工作频率改变，由自适应时钟发生电路输出的自适应时钟信号的频率改变，并且改变方向 自适应时钟信号的频率与最大可工作频率的频率一致。 时钟电路和方法可用于数字电路的设计或制造。

公开(公告)号：US20120139596A1

公开(公告)日：2012-06-07

申请号：US13311069

申请日：2011-12-05

申请人： Shiming He ,  Liqian Chen ,  Cong Yao ,  Xiang Li ,  Yu Liu ,  Jiayin Lu

发明人： Shiming He ,  Liqian Chen ,  Cong Yao ,  Xiang Li ,  Yu Liu ,  Jiayin Lu

IPC分类号： H03L7/085

CPC分类号： H03L7/0997

摘要： The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.

摘要翻译： 本发明提供一种提供时钟信号的时钟电路和方法。 时钟电路包括：自适应时钟产生电路，被配置为输出自适应时钟信号; 以及自适应时钟驱动电路，被配置为由自适应时钟信号驱动工作。 自适应时钟驱动电路的最大可工作频率高于或等于自适应时钟信号的频率。 当自适应时钟驱动电路的工作状态改变时，自适应时钟驱动电路的最大可工作频率改变，由自适应时钟发生电路输出的自适应时钟信号的频率改变，并且改变方向 自适应时钟信号的频率与最大可工作频率的频率一致。 时钟电路和方法可用于数字电路的设计或制造。

公开(公告)号：US20110179207A1

公开(公告)日：2011-07-21

申请号：US13007332

申请日：2011-01-14

申请人： Cong Yao ,  Qiwei Liu ,  Yu Liu ,  Xiang Li ,  Liqian Chen ,  Shiming He ,  Jiayin Lu

发明人： Cong Yao ,  Qiwei Liu ,  Yu Liu ,  Xiang Li ,  Liqian Chen ,  Shiming He ,  Jiayin Lu

IPC分类号： G06F13/14

CPC分类号： G06F13/382

摘要： A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).

摘要翻译： 提供了可变频率总线适配器，可变频率总线适配方法和可变频率总线适配系统。 该方法包括：根据由总线端发送的动态频率缩放（DFS）请求信号产生总线阻塞指示; 根据总线阻塞指示阻止当前总线传输; 并且在阻止当前总线传输之后将DFS响应信号反馈给总线侧，其中DFS响应信号适于使总线端执行DFS操作。 在该方法中，在DFS期间暂时阻塞总线传输，从而在不增加系统的时钟域数量或修改外围组件的情况下减少总线DFS期间由不稳定总线块引起的对外围组件的不良影响，从而减少 实现系统的复杂性，并提高动态电压频率缩放（DVFS）的适用性。

公开(公告)号：US20090323930A1

公开(公告)日：2009-12-31

申请号：US12375095

申请日：2007-07-19

申请人： Jiayin Lu ,  Jun Cao ,  Zhenhai Huang ,  Xiang Yan

发明人： Jiayin Lu ,  Jun Cao ,  Zhenhai Huang ,  Xiang Yan

IPC分类号： H04L9/28

CPC分类号： H04L9/0625 ,  H04L2209/80

摘要： An encrypting/decrypting processing method for implementing SMS4 algorithm in high efficiency is provided. After preparing constant array, input external data into register section, firstly make primary data conversion and then make secondary data conversion, finally repeat data conversion course until complete all specified data conversion courses and obtain processing result of circulating data encryption/decryption. And it solves the technical problems of data conversion in the background technique that number of circulating times is large and encrypting efficiency is low, simplifying the chip design, largely optimizing integrity of chip signal and being able to improve interference immunity of system and reduce system cost.

摘要翻译： 提供了一种以高效率实现SMS4算法的加密/解密处理方法。 准备常数阵列后，将外部数据输入到寄存器部分，首先进行主数据转换，然后进行二次数据转换，最后重复数据转换过程，直到完成所有指定的数据转换课程，并获得循环数据加密/解密的处理结果。 解决了循环次数大，加密效率低的背景技术数据转换技术问题，简化了芯片设计，大大提高了芯片信号的完整性，提高了系统的抗干扰能力，降低了系统成本 。

公开(公告)号：US20120219149A1

公开(公告)日：2012-08-30

申请号：US13465411

申请日：2012-05-07

申请人： JIAYIN LU ,  JUN CAO ,  XIANG YAN ,  ZHENHAI HUANG

发明人： JIAYIN LU ,  JUN CAO ,  XIANG YAN ,  ZHENHAI HUANG

IPC分类号： G06F21/24

CPC分类号： G09C1/00 ,  H04L9/0625 ,  H04L9/14 ,  H04L2209/125

摘要： An encryption and decryption processing system for achieving SMS4 cryptographic procedure can be provided. The system includes a repeating encryption and decryption data processing device comprising a first constant array storing unit, a first data registering unit and a first data converting unit. The first constant array storing unit stores a first constant array and send it to N-data converting sub-units of the first data converting unit. The first data registering unit registers data, deliver the registered data to a first data converting sub-unit. The N-data converting sub-units perform a data conversion processing, and transmit the obtained conversion data to a next data converting sub-unit for subsequent processing until the data conversion processing processes are completed, a particular number of the completed processed being equal to a value of a data depth.

摘要翻译： 可以提供用于实现SMS4密码过程的加密和解密处理系统。 该系统包括重复的加密和解密数据处理装置，包括第一常数阵列存储单元，第一数据登记单元和第一数据转换单元。 第一常数阵列存储单元存储第一常数阵列并将其发送到第一数据转换单元的N数据转换子单元。 第一数据登记单元登记数据，将注册的数据传送到第一数据转换子单元。 N数据转换子单元执行数据转换处理，并将所获得的转换数据发送到下一个数据转换子单元，用于后续处理，直到数据转换处理完成，完成处理的特定数量等于 数据深度的值。

公开(公告)号：US08175264B2

公开(公告)日：2012-05-08

申请号：US12281144

申请日：2007-02-27

申请人： Jiayin Lu ,  Jun Cao ,  Xiang Yan ,  Zhenhai Huang

发明人： Jiayin Lu ,  Jun Cao ,  Xiang Yan ,  Zhenhai Huang

IPC分类号： H04K1/00

CPC分类号： G09C1/00 ,  H04L9/0625 ,  H04L9/14 ,  H04L2209/125

摘要： An encryption and decryption processing method, system and computer-accessible medium for achieving SMS4 cryptographic procedure/algorithm can be provided. First, constant arrays can prepared, the external data are input into a data registering unit and the first data conversion is addressed. Secondly, the second data conversion is addressed. Thirdly, the second data conversion is repeated until completing all the prescribed data conversion. Then, the results of repeating encryption and decryption processing are achieved.

摘要翻译： 可以提供用于实现SMS4密码过程/算法的加密和解密处理方法，系统和计算机可访问介质。 首先，可以准备常数阵列，外部数据被输入到数据注册单元中，并且第一个数据转换被寻址。 其次，第二个数据转换被解决。 第三，重复第二次数据转换，直到完成所有规定的数据转换。 然后，实现重复加密和解密处理的结果。