Abstract:
An encrypting/decrypting processing method for implementing SMS4 algorithm in high efficiency is provided. After preparing constant array, input external data into register section, firstly make primary data conversion and then make secondary data conversion, finally repeat data conversion course until complete all specified data conversion courses and obtain processing result of circulating data encryption/decryption. And it solves the technical problems of data conversion in the background technique that number of circulating times is large and encrypting efficiency is low, simplifying the chip design, largely optimizing integrity of chip signal and being able to improve interference immunity of system and reduce system cost.
Abstract:
An encrypting/decrypting processing method for implementing SMS4 algorithm in high efficiency is provided. After preparing constant array, input external data into register section, firstly make primary data conversion and then make secondary data conversion, finally repeat data conversion course until complete all specified data conversion courses and obtain processing result of circulating data encryption/decryption. And it solves the technical problems of data conversion in the background technique that number of circulating times is large and encrypting efficiency is low, simplifying the chip design, largely optimizing integrity of chip signal and being able to improve interference immunity of system and reduce system cost.
Abstract:
An encryption and decryption processing method, system and computer-accessible medium for achieving SMS4 cryptographic procedure/algorithm can be provided. First, constant arrays can prepared, the external data are input into a data registering unit and the first data conversion is addressed. Secondly, the second data conversion is addressed. Thirdly, the second data conversion is repeated until completing all the prescribed data conversion. Then, the results of repeating encryption and decryption processing are achieved.
Abstract:
An encryption and decryption processing method of achieving SMS4 cryptographic algorithm and a system thereof are disclosed. Firstly, the method prepares constant arrays, inputs the external data into a data registering unit and deals with the first data conversion; secondly, deals with the second data conversion; thirdly, repeats the second data conversion, until completing all the prescribed data conversion, and then achieving the results of repeating encryption and decryption processing.
Abstract:
An encryption and decryption processing system for achieving SMS4 cryptographic procedure can be provided. The system includes a repeating encryption and decryption data processing device comprising a first constant array storing unit, a first data registering unit and a first data converting unit. The first constant array storing unit stores a first constant array and send it to N-data converting sub-units of the first data converting unit. The first data registering unit registers data, deliver the registered data to a first data converting sub-unit. The N-data converting sub-units perform a data conversion processing, and transmit the obtained conversion data to a next data converting sub-unit for subsequent processing until the data conversion processing processes are completed, a particular number of the completed processed being equal to a value of a data depth.
Abstract:
A block cipher algorithm based encryption processing method comprises the following steps: external key registration, external data registration, key expansion, data encryption conversion, internal data registration, and data iteration processing, which solves the problems of the prior ciphering method based on block cipher algorithm, such as low ciphering efficiency and high implementation cost, and efficiently reduces the resource consumption under the premise of keeping the high efficiency of the prior art, thereby reducing the implementation cost of the device. When the number of the conversion component is 1, the resource consumption is only about 60 percent of the prior art; and when the number of the conversion component is 2, the resource consumption is only about 70 percent of the prior art. The present invention increases a sub-key registration unit, which can reduce the critical paths and increase the clock dominant frequency of the ciphering equipment during the implementation of integrated circuits, thereby improving the ciphering capacity of the inventive method.
Abstract:
A packet cipher algorithm based encryption processing device includes a key expand unit and an encryption unit. The key expand unit comprises a key expand unit data registration component and at least one key expand unit data conversion component. The encryption unit comprises an encryption unit data registration component and at least one encryption unit data conversion component, and the number of the encryption unit data conversion component is the same as that of the key expand unit data conversion component, and besides, they are one to one. A sub-key output of each key expand unit data conversion component connects the corresponding sub-key input of each encryption unit data conversion component to solve the technical problems that the encryption efficiency of the prior packet cipher algorithm based encryption processing device is low and the cost is high. The advantage of the present invention is reducing the resource consumption and further reducing the achievement cost of the device under the premise of keeping the high efficiency of the prior art.
Abstract:
A block cipher algorithm based encryption processing method comprises the following steps: external key registration, external data registration, key expansion, data encryption conversion, internal data registration, and data iteration processing, which solves the problems of the prior ciphering method based on block cipher algorithm, such as low ciphering efficiency and high implementation cost, and efficiently reduces the resource consumption under the premise of keeping the high efficiency of the prior art, thereby reducing the implementation cost of the device. When the number of the conversion component is 1, the resource consumption is only about 60 percent of the prior art; and when the number of the conversion component is 2, the resource consumption is only about 70 percent of the prior art. The present invention increases a sub-key registration unit, which can reduce the critical paths and increase the clock dominant frequency of the ciphering equipment during the implementation of integrated circuits, thereby improving the ciphering capacity of the inventive method.
Abstract:
A packet cipher algorithm based encryption processing device includes a key expand unit and an encryption unit. The key expand unit comprises a key expand unit data registration component and at least one key expand unit data conversion component. The encryption unit comprises an encryption unit data registration component and at least one encryption unit data conversion component, and the number of the encryption unit data conversion component is the same as that of the key expand unit data conversion component, and besides, they are one to one. A sub-key output of each key expand unit data conversion component connects the corresponding sub-key input of each encryption unit data conversion component to solve the technical problems that the encryption efficiency of the prior packet cipher algorithm based encryption processing device is low and the cost is high. The advantage of the present invention is reducing the resource consumption and further reducing the achievement cost of the device under the premise of keeping the high efficiency of the prior art.
Abstract:
FIG. 1 is a top perspective view of a mini round ice tray, showing my new design; FIG. 2 is a bottom perspective view thereof; FIG. 3 is a front view thereof; FIG. 4 is a rear view thereof; FIG. 5 is a left side view thereof; FIG. 6 is a right side view thereof; FIG. 7 is a top view thereof; FIG. 8 is a bottom view thereof; FIG. 9 is its split state diagram thereof; and, FIG. 10 is an enlarged detail view of area 10 in FIG. 1. The broken lines in the drawings illustrate the portions of the mini round ice tray, which form no part of the claimed design. The dash-dot-dash broken lines encircling the enlarged views are for annotative purposes only and form no part of the claim thereof.