公开(公告)号：US20120008419A1

公开(公告)日：2012-01-12

申请号：US13178895

申请日：2011-07-08

申请人： Joo Yun HA ,  Jae Kwan KWON

发明人： Joo Yun HA ,  Jae Kwan KWON

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C16/0483

摘要： A semiconductor memory device includes cells strings including memory cells and coupled between a common source line and bit lines, respectively, a peripheral circuit configured to store data in the memory cells or read data stored in the memory cells, a main voltage supply unit configured to generate operating voltages to be supplied to the peripheral circuit, a precharge voltage supply unit configured to generate a precharge voltage for precharging the bit lines, and a switching circuit configured to transfer the precharge voltage to the common source line and one of the bit lines when a bit line precharge operation is performed.

摘要翻译： 半导体存储器件包括分别包括存储器单元并且耦合在公共源极线和位线之间的单元串，外围电路，被配置为将数据存储在存储单元中或读取存储在存储单元中的数据;主电压提供单元， 产生要供给外围电路的工作电压;预充电电压供给单元，被配置为产生用于对位线进行预充电的预充电电压;以及开关电路，被配置为将预充电电压传送到公共源极线和位线之一， 执行位线预充电操作。

公开(公告)号：US08093932B2

公开(公告)日：2012-01-10

申请号：US12650954

申请日：2009-12-31

申请人： Jae Kwan Kwon ,  Sang Hwa Chung

发明人： Jae Kwan Kwon ,  Sang Hwa Chung

IPC分类号： H03L7/00

CPC分类号： H03K17/22

摘要： A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

摘要翻译： 半导体存储装置的上电复位信号生成电路包括：外部电压电平检测器，被配置为检测外部电压并产生外部电压检测信号; 带隙电压产生单元，被配置为响应于所述外部电压检测信号而产生带隙电压; 电平检测分压单元，被配置为根据带隙电压的电平分压外部电压并产生除法电压; 以及上电复位信号生成单元，被配置为将所述带隙电压的电平与所述分压的电平进行比较，并生成上电复位信号。

公开(公告)号：US20110128053A1

公开(公告)日：2011-06-02

申请号：US12650954

申请日：2009-12-31

申请人： Jae Kwan KWON ,  Sang Hwa Chung

发明人： Jae Kwan KWON ,  Sang Hwa Chung

IPC分类号： H03L7/00

CPC分类号： H03K17/22

摘要： A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

摘要翻译： 半导体存储装置的上电复位信号生成电路包括：外部电压电平检测器，被配置为检测外部电压并产生外部电压检测信号; 带隙电压产生单元，被配置为响应于所述外部电压检测信号而产生带隙电压; 电平检测分压单元，被配置为根据带隙电压的电平分压外部电压并产生除法电压; 以及上电复位信号生成单元，被配置为将所述带隙电压的电平与所述分压的电平进行比较，并生成上电复位信号。

公开(公告)号：US20100033233A1

公开(公告)日：2010-02-11

申请号：US12345075

申请日：2008-12-29

申请人： Jae Kwan Kwon

发明人： Jae Kwan Kwon

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  H02M3/073

摘要： A pumping voltage generating circuit in a semiconductor memory apparatus includes a voltage supplying unit configured to supply an external power supply voltage to a first node in response to a first transfer signal, a node control unit configured to couple the first node to a second node in response to a second transfer signal and to couple the second node to an output node in response to a third transfer signal, a first pumping unit configured to increase a voltage level on the first node through a pumping operation that is performed in response to a first oscillation signal and to control one of an amount of voltage increment and decrement on the first node in response to a first control signal, and a second pumping unit configured to increase a voltage level on the second node through a pumping operation that is performed in response to a second oscillation signal and to control one of an amount of voltage increment and decrement on the second node in response to a second control signal.

摘要翻译： 半导体存储装置中的泵浦电压产生电路包括：电压供给单元，被配置为响应于第一传送信号向第一节点提供外部电源电压;节点控制单元，被配置为将第一节点耦合到第二节点 响应于第二传送信号并且响应于第三传送信号将第二节点耦合到输出节点;第一抽运单元，被配置为通过泵送操作来增加第一节点上的电压电平，所述泵送操作响应于第一传送信号 并且响应于第一控制信号来控制第一节点上的电压增量和减量量中的一个;以及第二抽运单元，其被配置为通过响应中执行的泵送操作来增加第二节点上的电压电平 到第二振荡信号，并且响应于第二控制，控制第二节点上的电压增量和减量量中的一个 点燃

公开(公告)号：US20090219081A1

公开(公告)日：2009-09-03

申请号：US12266623

申请日：2008-11-07

申请人： Jae-Kwan KWON ,  Yee-Yul Kim

发明人： Jae-Kwan KWON ,  Yee-Yul Kim

IPC分类号： H02M3/139

CPC分类号： G11C5/145

摘要： An internal voltage generation circuit of semiconductor memory device includes a reference voltage generation unit configured to generate a reference voltage, and a pumping control unit configured to be enabled at every active mode, compare the reference voltage with a fed-back voltage of a pumping voltage terminal, and output a pumping enable signal based on a comparison result. A storage unit is configured to store and output the pumping enable signal outputted from the pumping control unit. A charge pumping unit is configured to drive the pumping voltage terminal by performing a charge pumping operation in response to the pumping enable signal outputted from the storage unit.

摘要翻译： 半导体存储器件的内部电压产生电路包括被配置为产生参考电压的参考电压产生单元和被配置为在每个激活模式下使能的泵浦控制单元，将参考电压与泵浦电压的反馈电压进行比较 并根据比较结果输出泵浦使能信号。 存储单元被配置为存储并输出从泵送控制单元输出的泵送使能信号。 电荷泵送单元被配置为通过响应于从存储单元输出的泵送使能信号执行电荷泵送操作来驱动泵浦电压端子。

公开(公告)号：US08441867B2

公开(公告)日：2013-05-14

申请号：US13270175

申请日：2011-10-10

申请人： Jae-Kwan Kwon

发明人： Jae-Kwan Kwon

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  H02M3/07

摘要： A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

摘要翻译： 一种用于在半导体存储装置中产生泵浦电压的电路包括：控制信号生成块，被配置为产生通过将测试信号的电压电平移位到第一驱动电压电平而获得的第一控制信号;电压施加部， 响应于第一传输信号向第一节点提供外部电压，第一电荷泵被配置为响应于振荡器信号将第一节点的电压电平升高第一预定电平，并且配置第一电压输出部分 响应于第一控制信号来选择第一连接单元和第二连接单元中的至少一个，并且当启用第二传输信号时，使用所选择的连接单元将第一节点与第二节点互连，其中第一泵送 电压通过第二节点输出。

公开(公告)号：US20120139621A1

公开(公告)日：2012-06-07

申请号：US13309792

申请日：2011-12-02

申请人： Jae Kwan KWON

发明人： Jae Kwan KWON

IPC分类号： G05F1/10

CPC分类号： G11C5/145

摘要： A voltage supply circuit includes a pump voltage generator for generating an input voltage by changing a power source voltage to a desired level and changing a level of the input voltage according to a rising time of an operating voltage.

摘要翻译： 电压提供电路包括：泵电压发生器，用于通过将电源电压改变到期望电平并根据工作电压的上升时间改变输入电压的电平来产生输入电压。

公开(公告)号：US08130012B2

公开(公告)日：2012-03-06

申请号：US12346213

申请日：2008-12-30

申请人： Jae-Kwan Kwon ,  Sung-Joo Ha

发明人： Jae-Kwan Kwon ,  Sung-Joo Ha

IPC分类号： H03K3/00

CPC分类号： H03K17/167 ,  H03K19/00361

摘要： A buffer circuit of a semiconductor integrated apparatus includes a control block configured to output a result of comparing an input voltage level and an output voltage level as a control signal, and a buffering block configured to generate an output voltage having the substantially same level as an input voltage in response to the control signal.

摘要翻译： 半导体集成装置的缓冲电路包括：控制块，被配置为输出将输入电压电平和输出电压电平进行比较的结果作为控制信号;以及缓冲块，被配置为产生具有与 响应于控制信号的输入电压。

公开(公告)号：US20120032724A1

公开(公告)日：2012-02-09

申请号：US13270175

申请日：2011-10-10

申请人： Jae Kwan Kwon

发明人： Jae Kwan Kwon

IPC分类号： H03L5/00

CPC分类号： G11C5/145 ,  H02M3/07

摘要： A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

摘要翻译： 一种用于在半导体存储装置中产生泵浦电压的电路包括：控制信号生成块，被配置为产生通过将测试信号的电压电平移位到第一驱动电压电平而获得的第一控制信号;电压施加部， 响应于第一传输信号向第一节点提供外部电压，第一电荷泵被配置为响应于振荡器信号将第一节点的电压电平升高第一预定电平，并且配置第一电压输出部分 响应于第一控制信号来选择第一连接单元和第二连接单元中的至少一个，并且当启用第二传输信号时，使用所选择的连接单元将第一节点与第二节点互连，其中第一泵送 电压通过第二节点输出。

公开(公告)号：US20090230997A1

公开(公告)日：2009-09-17

申请号：US12346213

申请日：2008-12-30

申请人： Jae Kwan Kwon ,  Sung Joo Ha

发明人： Jae Kwan Kwon ,  Sung Joo Ha

IPC分类号： H03K3/00

CPC分类号： H03K17/167 ,  H03K19/00361

摘要： A buffer circuit of a semiconductor integrated apparatus includes a control block configured to output a result of comparing an input voltage level and an output voltage level as a control signal, and a buffering block configured to generate an output voltage having the substantially same level as an input voltage in response to the control signal.

摘要翻译： 半导体集成装置的缓冲电路包括：控制块，被配置为输出将输入电压电平和输出电压电平进行比较的结果作为控制信号;以及缓冲块，被配置为产生具有与 响应于控制信号的输入电压。