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    Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units
    3.
    发明授权
    Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units 失效

    公开(公告)号：US06594753B2

    公开(公告)日：2003-07-15

    申请号：US09519524

    申请日：2000-03-06

    申请人： Jack Choquette ,  Norman K. Yeung

    发明人： Jack Choquette ,  Norman K. Yeung

    IPC分类号： G06F930

    CPC分类号： G06F9/3891 ,  G06F9/3836 ,  G06F9/3885

    摘要： A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

    Processor instruction used to determine whether to perform a memory-related trap
    4.
    发明申请
    Processor instruction used to determine whether to perform a memory-related trap 有权
    处理器指令用于确定是否执行内存相关的陷阱

    公开(公告)号：US20100153689A1

    公开(公告)日：2010-06-17

    申请号：US12658669

    申请日：2010-02-12

    申请人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F9/38 ,  G06F12/10

    CPC分类号： G06F12/0253 ,  G06F9/3004 ,  G06F9/3861 ,  G06F11/2236

    摘要： Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.

    摘要翻译： 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令，以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱，其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试，所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个，并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下，其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。

    Processor instruction used to determine whether to perform a memory-related trap
    7.
    发明授权
    Processor instruction used to determine whether to perform a memory-related trap 有权
    处理器指令用于确定是否执行内存相关的陷阱

    公开(公告)号：US07689782B1

    公开(公告)日：2010-03-30

    申请号：US11296195

    申请日：2005-12-06

    申请人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0253 ,  G06F9/30003

    摘要： An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.

    摘要翻译： 公开了处理器在确定是否执行陷阱时使用的指令。 所述指令包括识别所述指令的一个或多个比特的第一组以及与所述确定中使用的第一地址值相关联的一个或多个比特的第二组。 该确定不包括执行使用第一地址值来确定存储器访问的存储器位置的存储器访问。 该确定至少部分地基于以下中的多于一个：包含在第一地址值中的一组或多个标记位的组，至少部分地使用第一地址值的一个或多个位的矩阵项， 与第一地址值相关联的翻译后备缓冲器条目，第一地址值是否与堆栈分配的存储器相关联，以及第一地址值是否包括空值。

    Efficient Streaming of Un-Aligned Load/Store Instructions that Save Unused Non-Aligned Data in a Scratch Register for the Next Instruction
    8.
    发明申请
    Efficient Streaming of Un-Aligned Load/Store Instructions that Save Unused Non-Aligned Data in a Scratch Register for the Next Instruction 审中-公开
    在下一条指令的划痕寄存器中保存未对齐的非对齐数据的未对齐加载/存储指令的高效流

    公开(公告)号：US20070106883A1

    公开(公告)日：2007-05-10

    申请号：US11164011

    申请日：2005-11-07

    申请人： Jack Choquette

    发明人： Jack Choquette

    IPC分类号： G06F9/44

    CPC分类号： G06F9/30043 ,  G06F9/30036 ,  G06F9/3816 ,  G06F9/383

    摘要： A memory block with any source alignment is streamed into general-purpose registers (GPRs) as aligned data using a streaming load instruction. A streaming store instruction reads the aligned data from the GPRs and writes the data into memory with any destination alignment. Data is streamed from any source alignment to any destination alignment. Memory accesses are aligned to memory lines. The data is rotated using the offset within a memory line of the base address. The rotated data is stored in a scratch register for use by the next streaming load instruction. Rotated data just read from memory is combined with rotated data in the scratch register read by the last streaming load instruction to generate result data to load into the destination GPR. Streaming condition codes are set when the block's end is detected to disable future streaming instructions. Aligned memory accesses at full bandwidth read the un-aligned block.

    摘要翻译： 具有任何源对齐的存储器块使用流加载指令作为对齐数据流传输到通用寄存器（GPR）。 流存储指令从GPR读取对齐的数据，并将数据写入存储器中，并进行任何目标对齐。 数据从任何源对齐流传输到任何目标对齐。 存储器访问与存储器行对齐。 使用基地址的存储器行内的偏移来旋转数据。 旋转的数据被存储在临时寄存器中以供下一个流加载指令使用。 从内存中读取的旋转数据与上次流式加载指令读取的临时寄存器中的旋转数据相结合，生成要加载到目标GPR的结果数据。 当检测到块的结束以禁止将来的流指令时，设置流条件代码。 以完全带宽对齐的存储器访问读取未对齐的块。

    Method for coordinating information flow between components
    9.
    发明授权
    Method for coordinating information flow between components 有权
    协调组件之间的信息流的方法

    公开(公告)号：US07062767B1

    公开(公告)日：2006-06-13

    申请号：US09654718

    申请日：2000-09-05

    申请人： Dominic Paul McCarthy ,  Jack Choquette

    发明人： Dominic Paul McCarthy ,  Jack Choquette

    IPC分类号： G06F9/46

    CPC分类号： G06F13/36

    摘要： A method of efficiently coordinating the communication of data and commands between multiple entities in a system is disclosed. A transaction protocol enabling centralized scheduling of chains of data transfers in a system is disclosed.

    摘要翻译： 公开了一种在系统中的多个实体之间有效地协调数据和命令的通信的方法。 公开了一种能够集中调度系统中数据传输链的事务协议。

    Method for providing a synchronous communication and transaction between functions on an integrated circuit therefore the functions operate independently at their own optimized speeds
    10.
    发明授权
    Method for providing a synchronous communication and transaction between functions on an integrated circuit therefore the functions operate independently at their own optimized speeds 失效
    用于在集成电路上的功能之间提供同步通信和交易的方法，因此功能以其自身的优化速度独立地运行

    公开(公告)号：US06775788B1

    公开(公告)日：2004-08-10

    申请号：US09654717

    申请日：2000-09-05

    申请人： Dominic Paul McCarthy ,  Jack Choquette

    发明人： Dominic Paul McCarthy ,  Jack Choquette

    IPC分类号： G06F1342

    CPC分类号： H04L45/00 ,  H04L12/42

    摘要： The invention relates to the field of system on a chip, SoC, information processing architecture and particularly to the use of a homogenous, concurrent-communication interconnection architecture that allows a variety of different functions to be connected together and their full synergistic performance realized. The functions are decoupled from each other, allowing performance optimization of each function without regard for the other functions on the chip. The system data flow is coordinated using a overall system schedule allowing data interactions to be orchestrated efficiently.

    摘要翻译： 本发明涉及芯片上的系统领域，SoC，信息处理架构，特别涉及使用均匀的并发通信互连架构，其允许将各种不同功能连接在一起并实现其完全协同的性能。 这些功能相互分离，允许每个功能的性能优化，而不考虑芯片上的其他功能。 使用整个系统调度来协调系统数据流，从而有效地协调数据交互。