公开(公告)号：US07691719B2

公开(公告)日：2010-04-06

申请号：US11457726

申请日：2006-07-14

Applicant: Cheol-Ju Yun ,  Kang-Yoon Lee ,  In-Ho Nam

Inventor： Cheol-Ju Yun ,  Kang-Yoon Lee ,  In-Ho Nam

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L27/10855

Abstract: Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

Abstract translation: 具有存储节点的半导体器件的实施例包括设置在半导体衬底上的层间绝缘层; 布置在所述层间绝缘层中以与所述基板的预定部分接触的导电焊盘，所述导电焊盘的上部突出于所述层间绝缘层的上方; 设置在所述导电焊盘和所述层间绝缘层上的蚀刻停止层; 并且存储节点穿透蚀刻停止层并且设置在导电焊盘上。 在湿法蚀刻工艺期间，湿蚀刻剂的穿透路径被完全阻挡，从而去除了模具氧化物层。 因此，防止了由于潮湿蚀刻剂的渗透而导致的绝缘层的无意蚀刻，导致更坚固，更稳定的存储节点结构。

公开(公告)号：US20070015362A1

公开(公告)日：2007-01-18

申请号：US11457726

申请日：2006-07-14

Applicant: Cheol-Ju YUN ,  Kang-Yoon LEE ,  In-Ho NAM

Inventor： Cheol-Ju YUN ,  Kang-Yoon LEE ,  In-Ho NAM

IPC: H01L21/302

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L27/10855

Abstract: Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

Abstract translation: 具有存储节点的半导体器件的实施例包括设置在半导体衬底上的层间绝缘层; 布置在所述层间绝缘层中以与所述基板的预定部分接触的导电焊盘，所述导电焊盘的上部突出于所述层间绝缘层的上方; 设置在所述导电焊盘和所述层间绝缘层上的蚀刻停止层; 并且存储节点穿透蚀刻停止层并且设置在导电焊盘上。 在湿法蚀刻工艺期间，湿蚀刻剂的穿透路径被完全阻挡，从而去除了模具氧化物层。 因此，防止了由于潮湿蚀刻剂的渗透而导致的绝缘层的无意蚀刻，导致更坚固，更稳定的存储节点结构。

公开(公告)号：US5620917A

公开(公告)日：1997-04-15

申请号：US615087

申请日：1996-03-14

Applicant: Joo-young Yoon ,  In-ho Nam

Inventor： Joo-young Yoon ,  In-ho Nam

IPC: H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/105 ,  H01L27/10808

Abstract: In a semiconductor memory device having a novel structure of a wiring layer and a large capacitance capacitor and the manufacturing method therefor, on the transistor formed on the semiconductor substrate, a first conductive layer is formed extending along with the gate electrode of the transistor and connecting with the gate electrode, a storage electrode of a capacitor is formed on the first conductive layer by interposing the insulation film between the first conductive layer and the source region of the transistor, and a second conductive layer is formed in connection with the first conductive layer at a portion between memory cell array and the peripheral circuit region. Storage electrodes can be made thicker without affecting to the step-difference between memory cells and the peripheral circuit region, so that a more reliable semiconductor memory device with a capacitor having a larger capacitance can be realized.

Abstract translation: 在具有布线层和大容量电容器的新颖结构的半导体存储器件及其制造方法中，在形成在半导体衬底上的晶体管上形成有与晶体管的栅电极一起延伸的第一导电层， 通过在第一导电层和晶体管的源极区域之间插入绝缘膜，在第一导电层上形成电容器的存储电极，并且与第一导电层形成第二导电层 在存储单元阵列和外围电路区域之间的部分。 可以使存储电极变得更厚，而不会影响存储单元和外围电路区域之间的差分，从而可以实现具有较大电容的电容器的更可靠的半导体存储器件。

公开(公告)号：US20050272250A1

公开(公告)日：2005-12-08

申请号：US11147953

申请日：2005-06-07

Applicant: Cheol-Ju Yun ,  Tae-Young Chung ,  In-Ho Nam

Inventor： Cheol-Ju Yun ,  Tae-Young Chung ,  In-Ho Nam

IPC: H01L21/28 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L27/10885 ,  H01L21/486 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an embodiment a method of forming self-aligned contacts in a semiconductor memory device includes: forming conductive stacks of conductive layers on a semiconductor substrate; forming insulating spacer layers on sidewalls of the conductive stacks; forming an insulating layer; forming a capping insulating layer covering portions of the insulating layer; and forming conductive pads that fill the contact holes to contact the semiconductor substrate. The capping insulating layer has a function of a buffer, so an etched amount of mask layers insulating the conductive layers is minimized, and a probability of a short circuit between capacitor electrodes and the conductive stacks is greatly reduced.

Abstract translation: 在一个实施例中，在半导体存储器件中形成自对准触点的方法包括：在半导体衬底上形成导电层的导电层; 在导电叠层的侧壁上形成绝缘间隔层; 形成绝缘层; 形成覆盖所述绝缘层的部分的覆盖绝缘层; 以及形成填充接触孔以接触半导体衬底的导电焊盘。 封盖绝缘层具有缓冲器的功能，因此绝缘导电层的掩模层的蚀刻量最小化，电容器电极和导电叠层之间的短路的可能性大大降低。

公开(公告)号：US5728627A

公开(公告)日：1998-03-17

申请号：US747783

申请日：1996-11-14

Applicant: In-ho Nam ,  Won-seong Lee

Inventor： In-ho Nam ,  Won-seong Lee

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/7684

Abstract: A conductive planarization layer, preferably a doped polysilicon layer, is used as a planarization layer for forming a conductive interconnect, such as a memory device bit line, thereon. Etching of the doped polysilicon planarization layer may be accurately controlled to form a planarized layer of controlled thickness, without requiring high temperature reflow heating of boro-phospo-silicate glass which can degrade transistor parameters. In particular, an insulating layer is formed on spaced apart source and drain regions and on the gate therebetween. A doped polysilicon layer is formed on the insulating layer. The doped polysilicon layer is planarized. A contact hole is formed in the insulating layer and in the doped polysilicon layer, to thereby expose the source or drain region. A conductive interconnect is then formed in the contact hole and on the gate.

Abstract translation: 导电平坦化层，优选掺杂多晶硅层，用作形成诸如存储器件位线之类的导电互连的平坦化层。 可以精确地控制掺杂多晶硅平坦化层的蚀刻以形成受控厚度的平坦化层，而不需要可降解晶体管参数的硼磷硅酸盐玻璃的高温回流加热。 特别地，绝缘层形成在间隔开的源极和漏极区域上以及其间的栅极上。 在绝缘层上形成掺杂多晶硅层。 掺杂多晶硅层被平坦化。 在绝缘层和掺杂多晶硅层中形成接触孔，从而露出源区或漏区。 然后在接触孔和栅极上形成导电互连。

公开(公告)号：US5491103A

公开(公告)日：1996-02-13

申请号：US225287

申请日：1994-04-08

Applicant: Tae-hyuk Ahn ,  In-ho Nam ,  Joo-young Yoon

Inventor： Tae-hyuk Ahn ,  In-ho Nam ,  Joo-young Yoon

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/10817

Abstract: A method for manufacturing a capacitor structure of a highly integrated semiconductor memory device. A first conductive layer is formed on a semiconductor substrate, and a first pattern is formed on the first conductive layer. A first material layer is formed on the resultant structure whereon the first pattern is formed, and the first material layer is etched anisotropically, to thereby form a spacer on the side of the first pattern. After etching the first conductive layer using the spacer as an etch-mask, the first pattern is removed. A second conductive layer is formed on the resultant structure and etched anisotropically. The spacer is removed, to thereby form a storage electrode of a capacitor. The distance between neighboring capacitors can be minimized to a value smaller than the limitation imposed by the lithographic technique, to thereby maximize the area of the capacitor.

Abstract translation: 一种用于制造高度集成的半导体存储器件的电容器结构的方法。 第一导电层形成在半导体衬底上，第一图案形成在第一导电层上。 第一材料层形成在其上形成第一图案的所得结构上，并且第一材料层被各向异性地蚀刻，从而在第一图案侧形成间隔物。 在使用间隔物蚀刻第一导电层作为蚀刻掩模之后，第一图案被去除。 在所得结构上形成第二导电层并各向异性地进行蚀刻。 去除间隔物，从而形成电容器的存储电极。 相邻电容器之间的距离可以最小化为小于由光刻技术施加的限制的值，从而使电容器的面积最大化。

公开(公告)号：US06878614B2

公开(公告)日：2005-04-12

申请号：US10337540

申请日：2003-01-07

Applicant: Ho-won Sun ,  Kwang-kyu Bang ,  In-ho Nam

Inventor： Ho-won Sun ,  Kwang-kyu Bang ,  In-ho Nam

IPC: H01L21/82 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L21/44

CPC classification number: H01L27/10894 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.

Abstract translation: 形成集成电路器件的方法可以包括在集成电路衬底上形成多个熔丝，并且在集成电路衬底上和多个熔丝上形成绝缘层，使得熔丝在集成电路衬底之间 和绝缘层。 可以在绝缘层中形成多个保险丝切割孔，其中每个保险丝切割孔暴露在相应的一根熔丝上的目标点，并且可以在暴露的目标位置减小熔丝的横截面积 斑点。 还讨论了相关结构。

公开(公告)号：US5583356A

公开(公告)日：1996-12-10

申请号：US158851

申请日：1993-11-29

Applicant: Joo-young Yoon ,  In-ho Nam

Inventor： Joo-young Yoon ,  In-ho Nam

IPC: H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/105 ,  H01L27/10808

Abstract: In a semiconductor memory device having a novel structure of a wiring layer and a large capacitance capacitor and the manufacturing method therefor, on the transistor formed on the semiconductor substrate, a first conductive layer is formed extending along with the gate electrode of the transistor and connecting with the gate electrode, a storage electrode of a capacitor is formed on the first conductive layer by interposing the insulation film between the first conductive layer and the source region of the transistor, and a second conductive layer is formed in connection with the first conductive layer at a portion between memory cell array and the peripheral circuit region. Storage electrodes can be made thicker without affecting to the step-difference between memory cells and the peripheral circuit region, so that a more reliable semiconductor memory device with a capacitor having a larger capacitance can be realized.

Abstract translation: 在具有布线层和大容量电容器的新颖结构的半导体存储器件及其制造方法中，在形成在半导体衬底上的晶体管上形成有与晶体管的栅电极一起延伸的第一导电层， 通过在第一导电层和晶体管的源极区域之间插入绝缘膜，在第一导电层上形成电容器的存储电极，并且与第一导电层形成第二导电层 在存储单元阵列和外围电路区域之间的部分。 可以使存储电极变得更厚，而不会影响存储单元和外围电路区域之间的差分，从而可以实现具有较大电容的电容器的更可靠的半导体存储器件。