公开(公告)号：US08659456B2

公开(公告)日：2014-02-25

申请号：US13610808

申请日：2012-09-11

申请人： Hsiang-Hui Chang ,  Hsin-Hung Chen ,  Chi-Yun Wang ,  Chih-Jung Chen

发明人： Hsiang-Hui Chang ,  Hsin-Hung Chen ,  Chi-Yun Wang ,  Chih-Jung Chen

IPC分类号： H03M1/10

CPC分类号： H03K5/007 ,  H03M1/1009 ,  H03M1/1019 ,  H03M1/12

摘要： An embodiment of the invention provides an electronic device. The electronic device includes a digital-to-analog converter (DAC), a transmitter front-end (TX FE), an amplifier, an analog-to-digital converter (ADC), and a swap circuitry. The TX FE has a first and a second input end coupled to a first and a second output end of the DAC, respectively. The ADC has a first and a second input end coupled to a first and a second output end of the amplifier, respectively. The swap circuitry is configured to couple the first and second output ends of the DAC to a first and a second input end of the amplifier in a normal state, respectively, and couple the first and second output ends of the DAC to the second and first input ends of the amplifier in a swapped state, respectively.

摘要翻译： 本发明的实施例提供一种电子设备。 电子设备包括数模转换器（DAC），发射机前端（TX FE），放大器，模数转换器（ADC）和交换电路。 TX FE具有分别耦合到DAC的第一和第二输出端的第一和第二输入端。 ADC具有分别耦合到放大器的第一和第二输出端的第一和第二输入端。 交换电路被配置为分别将DAC的第一和第二输出端耦合到放大器的第一和第二输入端，并将DAC的第一和第二输出端耦合到第二和第一 放大器的输入端分别处于交换状态。

公开(公告)号：US08427243B2

公开(公告)日：2013-04-23

申请号：US13029130

申请日：2011-02-17

申请人： Hsin-Hung Chen ,  Hsiang-Hui Chang

发明人： Hsin-Hung Chen ,  Hsiang-Hui Chang

IPC分类号： H03B19/00

CPC分类号： H03C3/0925 ,  H03C3/0941 ,  H03C3/0958

摘要： A signal generating circuit includes: an operating circuit arranged to generate a first control signal according to a reference clock signal and a feedback oscillating signal; a controllable oscillator arranged to generate an output oscillating signal according to the first control signal and a second control signal; a feedback circuit arranged to generate the feedback oscillating signal according to the output oscillating signal and a third control signal; a control circuit arranged to generate the second control signal and the third control signal according to an input signal; and a calibrating circuit arranged to calibrate the control circuit to adjust the second control signal by detecting a phase difference between the reference clock signal and the feedback oscillating signal.

摘要翻译： 信号发生电路包括：操作电路，被配置为根据参考时钟信号和反馈振荡信号产生第一控制信号; 可控振荡器，被配置为根据第一控制信号和第二控制信号产生输出振荡信号; 反馈电路，被配置为根据输出振荡信号和第三控制信号产生反馈振荡信号; 控制电路，被配置为根据输入信号产生第二控制信号和第三控制信号; 以及校准电路，其布置成通过检测参考时钟信号和反馈振荡信号之间的相位差校准控制电路来调整第二控制信号。

公开(公告)号：US08395453B2

公开(公告)日：2013-03-12

申请号：US12235623

申请日：2008-09-23

申请人： Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

发明人： Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

IPC分类号： H03L7/08 ,  H03C3/06

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H03L2207/50

摘要： Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.

摘要翻译： 通过预测根据估计的量化误差预测的可能的相位误差来补偿全数字锁相环（ADPLL）内的时间 - 数字转换器（TDC）的相位误差，数字控制 振荡器（DCO），TDC的增益或其组合。 通过适当的导入，可能的相位误差可以由量化误差进一步指示，对应于具有TDC的TDC模块接收的参考周期的一半的代码方差，ADPLL的分频器的分频比，分数 与量化误差相关的数字或其组合。 数字相位误差消除模块还用于产生用于补偿TDC的相位误差的可能的相位误差。

公开(公告)号：US08354947B2

公开(公告)日：2013-01-15

申请号：US13025171

申请日：2011-02-11

申请人： Hsiang-Hui Chang ,  Caiyi Wang ,  George Chien ,  Hsin-Hung Chen ,  Chih-Jung Chen

发明人： Hsiang-Hui Chang ,  Caiyi Wang ,  George Chien ,  Hsin-Hung Chen ,  Chih-Jung Chen

IPC分类号： H03M3/00

CPC分类号： H03M3/344 ,  H03M3/436 ,  H03M3/50 ,  H03M7/3042

摘要： One signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is arranged to perform a notch filtering operation upon the signal output for generating a filtered signal output. Another signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is enabled for performing a notch filtering operation upon the signal output when the signal processing apparatus operates in a first operational mode, and the notch filtering block is disabled when the signal processing apparatus operates in a second operational mode.

摘要翻译： 一个信号处理装置包括Σ-Δ调制块和陷波滤波块。 Σ-Δ调制块被布置成在信号输入端执行Σ-Δ调制，从而产生信号输出。 陷波滤波块被布置成在信号输出上执行陷波滤波操作以产生滤波信号输出。 另一信号处理装置包括Σ-Δ调制块和陷波滤波块。 Σ-Δ调制块被布置成在信号输入端执行Σ-Δ调制，从而产生信号输出。 当信号处理装置在第一操作模式下操作时，陷波滤波块被使能以对信号输出执行陷波滤波操作，并且当信号处理装置在第二操作模式下操作时，陷波滤波块被禁用。

公开(公告)号：US08228128B2

公开(公告)日：2012-07-24

申请号：US12838502

申请日：2010-07-19

申请人： Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

发明人： Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

IPC分类号： H03L7/085

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H03L2207/50

摘要： For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

摘要翻译： 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。

公开(公告)号：US20120033719A1

公开(公告)日：2012-02-09

申请号：US13275068

申请日：2011-10-17

申请人： Hsin-Hung Chen ,  Hsiang-Hui Chang ,  Chun-Pang Wu

发明人： Hsin-Hung Chen ,  Hsiang-Hui Chang ,  Chun-Pang Wu

IPC分类号： H04L27/36 ,  H04B17/00

CPC分类号： H03C5/00

摘要： A transmitter for transmitting and calibrating a phase signal and an amplitude signal. The transmitter comprises a phase modulation path, an amplitude modulation path, and a control unit. The phase modulation path transmits the phase signal. The amplitude modulation path transmits the amplitude signal. The control unit delays the signal on at least one of the phase modulation path and the amplitude modulation.

摘要翻译： 用于发送和校准相位信号和振幅信号的发射机。 发射机包括相位调制路径，幅度调制路径和控制单元。 相位调制路径发送相位信号。 振幅调制路径发送振幅信号。 控制单元将信号延迟至相位调制路径和振幅调制中的至少一个。

公开(公告)号：US20110254635A1

公开(公告)日：2011-10-20

申请号：US13170860

申请日：2011-06-28

申请人： Ping-Ying Wang ,  Hsiang-Hui Chang

发明人： Ping-Ying Wang ,  Hsiang-Hui Chang

IPC分类号： H03L7/099

CPC分类号： H03L7/099 ,  H03L7/16

摘要： An oscillating circuit including a digital sigma-delta modulator and a controlled oscillator is disclosed. The digital sigma-delta modulator receives a fractional bit signal to generate a control signal. The controlled oscillator includes a varactor dynamically coupled to receive the control signal.

摘要翻译： 公开了一种包括数字Σ-Δ调制器和受控振荡器的振荡电路。 数字Σ-Δ调制器接收分数位信号以产生控制信号。 受控振荡器包括动态耦合以接收控制信号的变容二极管。

公开(公告)号：US07827432B2

公开(公告)日：2010-11-02

申请号：US12169621

申请日：2008-07-08

申请人： Hsiang-Hui Chang

发明人： Hsiang-Hui Chang

IPC分类号： G06F1/04

CPC分类号： H03L7/0891

摘要： Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller.

摘要翻译： 提供了具有有限输出脉冲宽度的相位频率检测器和相关方法。 在示例性相位频率检测器上，包括第一边缘检测器，第二边缘检测器和脉冲整形控制器。 第一边缘检测器用于检测第一信号的第一类型边缘以产生第一检测信号。 第二边缘检测器用于检测第二信号的第一类型边缘以产生第二检测信号。 所述脉冲整形控制器用于接收所述第一检测信号和所述第二检测信号，并用于产生到所述第一边缘检测器的第一控制信号并产生到所述第二边缘检测器的第二控制信号。 此外，脉冲整形控制器还产生第一输出信号和第二输出信号，其中第一输出信号的脉冲宽度被脉冲整形控制器限制。

公开(公告)号：US20100151802A1

公开(公告)日：2010-06-17

申请号：US12335540

申请日：2008-12-16

申请人： Hsin-Hung Chen ,  Hsiang-Hui Chang ,  Chun-Pang Wu ,  Yung-Yu Lin ,  Jong-Woei Chen

发明人： Hsin-Hung Chen ,  Hsiang-Hui Chang ,  Chun-Pang Wu ,  Yung-Yu Lin ,  Jong-Woei Chen

IPC分类号： H04B1/02

CPC分类号： H04B1/04 ,  H03C5/00 ,  H04B2001/0491

摘要： An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

摘要翻译： 提供极性发射机中的幅度调制电路和用于校准极性发射机中的振幅偏移的方法。 幅度调制电路包括数模转换器（DAC），低通滤波器（LPF），gm级和校准模块。 DAC耦合到幅度调制信号输入端。 LPF耦合到DAC，并且gm级耦合到LPF。 校准模块具有耦合到gm级的输入，以及耦合到DAC和gm级之间路径上的节点的输出。 该方法包括：根据从gm级产生的幅度调制信号产生振幅偏移校准信号; 以及经由校准模块的输出将幅度偏移校准信号发送到DAC和gm级之间的路径上的节点，以便校准振幅偏移。

公开(公告)号：US07728686B2

公开(公告)日：2010-06-01

申请号：US12235606

申请日：2008-09-23

申请人： Jing-Hong Conan Zhan ,  Ping-Ying Wang ,  Hsiang-Hui Chang

发明人： Jing-Hong Conan Zhan ,  Ping-Ying Wang ,  Hsiang-Hui Chang

IPC分类号： H03B5/12 ,  H03B5/18 ,  H03L7/085 ,  H03L7/099

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H03L2207/50

摘要： A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

摘要翻译： 数字控制振荡器（DCO）用于全数字锁相环，用于消除频率不连续性。 DCO包括罐模块和负gm单元。 所述箱模块包括多个单元，所述单元的至少一部分包括用于分别处理奇数位或偶位的第一跟踪集和第二跟踪集。 奇数位和偶位与整数信号，分数信号或其组合相关，分数信号由输入到DCO的初级电压表示。 使用DCO，消除了频率不连续性和不期望的刺激。