公开(公告)号：US06510474B1

公开(公告)日：2003-01-21

申请号：US09439866

申请日：1999-11-12

申请人： Henry Stracovsky ,  Piotr Szabelski

发明人： Henry Stracovsky ,  Piotr Szabelski

IPC分类号： G06F1300

CPC分类号： G06F13/1621 ,  G06F12/0215 ,  G06F13/1626

摘要： According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests are described. In one embodiment, a method of increasing data bandwidth by reordering incoming memory requests in order to avoid gaps between commands on a command bus and data packets on a data bus while maintaining the original incoming memory request order is disclosed. A best position in a command queue is calculated for each new incoming command by a reordering block coupled to the command queue. Read data is stored in a data queue while the associated incoming commands are stored in their respective original order in a FIFO register included in a re-reordering block. The data is stored in its original order in a data queue while incoming data from the memory is stored in a read-data buffer included in the re-reordering block according to the order stored in the data queue. The stored commands are sent to the processor according to the order stored in the FIFO such that the data to the processor will be issued in the same order as incoming from processor commands.

摘要翻译： 根据本发明，描述了为了恢复无序存储器请求的原始顺序来重新排序命令和数据分组的技术。 在一个实施例中，公开了一种通过重新排序进入的存储器请求来增加数据带宽的方法，以便避免在命令总线上的命令与数据总线上的数据分组之间的间隙，同时保持原始输入存储器请求顺序。 通过耦合到命令队列的重新排序块，为每个新的传入命令计算命令队列中的最佳位置。 读取数据被存储在数据队列中，而相关联的输入命令以它们各自的原始顺序存储在包括在重新排序块中的FIFO寄存器中。 根据存储在数据队列中的顺序，将数据以原始顺序存储在数据队列中，同时来自存储器的输入数据被存储在包含在重新排序块中的读数据缓冲器中。 存储的命令根据存储在FIFO中的顺序发送到处理器，使得到与处理器命令相同的顺序向处理器发送数据。

公开(公告)号：US06286075B1

公开(公告)日：2001-09-04

申请号：US09439715

申请日：1999-11-12

申请人： Henry Stracovsky ,  Piotr Szabelski

发明人： Henry Stracovsky ,  Piotr Szabelski

IPC分类号： G06F1300

CPC分类号： G06F12/0215

摘要： A method of using a reduced number of page tag registers to track a state of physical pages in memory systems are is described. An incoming system address request is received that includes a requested bank number and a requested page number. A page register located in memory controller corresponding to the requested bank number is then located and the stored page address included in the located page register is then compared to the requested page address. The requested page in the memory bank corresponding to the requested bank number is then accessed when the stored page address matches the requested page address for the requested memory bank. The stored page using page address from the page register of the bank which number is given by random page register number generator is closed if the requested bank and stored page address do not match. However, a new page using the page address from the incoming system address is opened after which the requested bank is accessed. Furthermore, the memory controller includes an adjustable comparator unit coupled to each of the plurality of page registers.

摘要翻译： 描述了使用减少数量的页面标签寄存器来跟踪存储器系统中的物理页面的状态的方法。 接收到包括所请求的银行号码和所请求的页码的输入系统地址请求。 然后，位于与所请求的库号相对应的存储器控​​制器中的页寄存器被定位，并且包含在所位于页寄存器中的存储的页地址然后与所请求的页地址进行比较。 当所存储的页面地址与所请求的存储体的所请求的页面地址匹配时，访问对应于所请求的库号的存储器库中的所请求的页面。 如果所请求的银行和存储的页面地址不匹配，则使用页面寄存器的存储页面使用页面寄存器，该编号由随机页面寄存器号码生成器给出。 但是，使用来自传入系统地址的页面地址的新页面将被打开，之后访问所请求的存储区。 此外，存储器控制器包括耦合到多个页寄存器中的每一个的可调比较器单元。

公开(公告)号：US20110320913A1

公开(公告)日：2011-12-29

申请号：US12824299

申请日：2010-06-28

申请人： Henry Stracovsky ,  Michael Espig ,  Victor W. Lee ,  Daehyun Kim

发明人： Henry Stracovsky ,  Michael Espig ,  Victor W. Lee ,  Daehyun Kim

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1012 ,  H03M7/30 ,  H03M7/3082 ,  H03M7/6064 ,  H03M13/6312 ,  H03M13/6505 ,  H03M13/6566

摘要： Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.

摘要翻译： 用于纠错的方法和装置。 接收要存储在存储装置中的N位块数据。 存储器件不执行任何纠错码（ECC）算法，也不为N位数据块提供指定的纠错码存储。 数据压缩应用于N位数据以压缩数据块以产生M位压缩数据块。 针对M位压缩数据计算K位ECC，其中M + K小于或等于N.M位压缩数据和K位ECC一起存储在存储器件中。

公开(公告)号：US06430642B1

公开(公告)日：2002-08-06

申请号：US09723750

申请日：2000-11-27

申请人： Henry Stracovsky ,  Piotr Szabelski

发明人： Henry Stracovsky ,  Piotr Szabelski

IPC分类号： G06F1200

CPC分类号： G06F13/1605 ,  G06F12/0215 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1642

摘要： According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of requesting device requests of the external devices, a request queue controller unit coupled to the request queue suitably arranged to fetch any of the requests stored therein, a responds queue suitably arranged to store any number of responses from the external devices. The apparatus also includes a responds queue controller unit coupled to the responds queue suitably arranged to fetch any of the requests stored therein; wherein each of the responds and its associated request have associated with them a group identification number indicating a particular group of requesting devices from which the request originated and the corresponding response is destined, wherein the responds queue controller and the request queue controller units use a priority number stored in a group priority selector register to prioritize each of the stored requests and responses, such that a request or response having a higher priority bypasses a request or response having a lower priority.

摘要翻译： 根据本发明，用于对访问外部设备进行优先级排序的装置包括适当地布置成存储外部设备的任何数量的请求设备请求的请求队列，耦合到请求队列的请求队列控制器单元，其适当地布置成获取 存储在其中的请求，适当地布置成存储来自外部设备的任何数量的响应的响应队列。 所述设备还包括响应队列控制器单元，其耦合到所述响应队列，所述响应队列被适当地布置成获取存储在其中的任何请求; 其中所述响应及其相关联的请求中的每一个与它们相关联，指示来自所述请求的特定请求设备组的组标识号和所述相应的响应被发往，其中所述响应队列控制器和所述请求队列控制器单元使用优先级 存储在组优先选择器寄存器中以对每个存储的请求和响应进行优先级排序，使得具有较高优先级的请求或响应绕过具有较低优先级的请求或响应。

公开(公告)号：US06385708B1

公开(公告)日：2002-05-07

申请号：US09439857

申请日：1999-11-12

申请人： Henry Stracovsky ,  Piotr Szabelski

发明人： Henry Stracovsky ,  Piotr Szabelski

IPC分类号： G06F1200

CPC分类号： G06F13/1626 ,  G06F12/0215 ,  G06F13/1605 ,  G06F13/1621

摘要： According to the present invention, a scheduler that uses a timing-look-up-table and page timers to determine the time between two consecutive memory accesses is described. The scheduler for scheduling a plurality of commands to an associated memory, the memory comprising a plurality of M memory banks and a plurality of N memory pages includes restriction circuitry for determining an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank and reordering circuitry for determining an order in which the commands should be transmitted to the associated memory with reference to the earliest issue time associated with each command and a data occurrence time associated with selected ones of the commands.

摘要翻译： 根据本发明，描述了使用定时查找表和寻呼定时器来确定两个连续存储器访问之间的时间的调度器。 用于将多个命令调度到相关联的存储器的调度器，所述存储器包括多个M个存储器组和多个N个存储器页面，所述存储器包括限制电路，用于至少部分地基于与所述存储器相关联的访问延迟来确定每个命令的最早发布时间 参考与每个命令相关联的最早发布时间，以及与所选择的命令相关联的数据发生时间，与对应于相同存储体和命令电路的命令的其他命令相对应的数据发生时间 命令。

公开(公告)号：US06216178B1

公开(公告)日：2001-04-10

申请号：US09439276

申请日：1999-11-12

申请人： Henry Stracovsky ,  Piotr Szabelski

发明人： Henry Stracovsky ,  Piotr Szabelski

IPC分类号： G06F1200

CPC分类号： G06F13/1621 ,  G06F12/0215 ,  G06F13/1605 ,  G06F13/1626

摘要： According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus.

摘要翻译： 根据本发明，公开了一种基于目标响应限制来重新排序命令以实现最佳命令序列的系统。 耦合到命令队列的数据队列被布置为存储指示何时数据传输将在控制器之间的数据总线上出现在已经发出的对目标设备的请求上的时间，并且被布置为存储突发位和读/ 写位（r / w）。 该系统还包括耦合到数据队列的冲突检测器和命令队列，用于检测存储在命令队列中的发出的命令与已经发出的存储在数据队列中的命令之间的数据总线上的可能冲突。 队列和链路控制器耦合到冲突检测器和数据队列和命令队列，并且被布置成存储和重新排序要发出的命令，其中控制器计算命令的新发布时间以及数据出现在时间上 数据总线。

公开(公告)号：US20140181618A1

公开(公告)日：2014-06-26

申请号：US13727561

申请日：2012-12-26

申请人： Wei Wu ,  Shih-Lien L. Lu ,  Rajat Agarwal ,  Henry Stracovsky

发明人： Wei Wu ,  Shih-Lien L. Lu ,  Rajat Agarwal ,  Henry Stracovsky

IPC分类号： H03M13/15

CPC分类号： H03M13/151 ,  H03M13/036 ,  H03M13/11 ,  H03M13/152 ,  H03M13/373 ,  H03M13/616

摘要： Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

摘要翻译： 描述用于错误检测和校正的装置和方法的实施例。 码字可以具有数据部分和相关联的校验位。 在实施例中，一个或多个错误检测模块可以被配置为检测码字中的多个错误类型。 与一个或多个错误检测模块耦合的一个或多个错误校正模块还可以被配置为一旦一个或多个错误检测模块检测到，则校正多个错误类型的错误。 可以描述和/或要求保护其他实施例。

公开(公告)号：US06539440B1

公开(公告)日：2003-03-25

申请号：US09439867

申请日：1999-11-12

申请人： Henry Stracovsky ,  Piotr Szabelski

发明人： Henry Stracovsky ,  Piotr Szabelski

IPC分类号： G06F1314

CPC分类号： G06F13/161 ,  G06F12/0215

摘要： According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page timers such that each of the page timers store a period of time between a last issued command to the particular page and a predicted next access to the memory, wherein the next access to the same page can be “close”, “open”, “write” or “read”. An incoming new command is received and it is then determined how long a particularly page access has to wait before the issue. An appropriate contents of a command timing lookup table is selected by the new command. A new time value is written into appropriate page timers that has to be inserted between the new command and a possible next access to the same page.

摘要翻译： 根据本发明，公开了一种用于非常快速地计算由存储器控制器发出的新命令的最早命令发布时间的方法。 存储器控制器包括N页状态寄存器，每个页状态寄存器包括四个页定时器，使得每个页定时器存储在最后发出的命令与特定页之间的时间段以及对存储器的预测的下一访问，其中下一访问 相同的页面可以是“关闭”，“打开”，“写入”或“读取”。 接收到新的命令，然后确定特定页面访问在发布之前必须等待多长时间。 命令定时查找表的适当内容由新命令选择。 将新的时间值写入适当的页面定时器，必须在新命令和可能的下一次访问同一页面之间插入。

公开(公告)号：US06442666B1

公开(公告)日：2002-08-27

申请号：US09491408

申请日：2000-01-26

申请人： Henry Stracovsky

发明人： Henry Stracovsky

IPC分类号： G06F1210

CPC分类号： G06F12/1045 ,  G06F12/0802 ,  G06F12/0893 ,  G06F12/1027 ,  G06F13/161

摘要： According to the present invention, methods and apparatus for reducing memory access latency are disclosed. When a new entry is made to translation look aside buffer, the new TLB entry points to a corresponding TLB page of memory. Concurrently with the updating of the TLB, the TLB page is moved temporally closer to a processor by storing the TLB page in a TLB page cache. The TLB page cache is temporally closer to the processor than is a main memory.

摘要翻译： 根据本发明，公开了用于减少存储器访问等待时间的方法和装置。 当一个新条目作为翻译旁边缓冲区时，新的TLB条目指向对应的内存的TLB页面。 与TLB的更新同时，通过将TLB页面存储在TLB页面高速缓存中，TLB页面在时间上移动到更接近处理器。 TLB页面缓存在时间上比主存储器更接近于处理器。

公开(公告)号：US06442644B1

公开(公告)日：2002-08-27

申请号：US09132158

申请日：1998-08-10

申请人： David B. Gustavson ,  David V. James ,  Hans A. Wiggers ,  Peter B. Gillingham ,  Cormac M. O'Connell ,  Bruce Millar ,  Jean Crepeau ,  Kevin J. Ryan ,  Terry R. Lee ,  Brent Keeth ,  Troy A. Manning ,  Donald N. North ,  Desi Rhoden ,  Henry Stracovsky ,  Yoshikazu Morooka

发明人： David B. Gustavson ,  David V. James ,  Hans A. Wiggers ,  Peter B. Gillingham ,  Cormac M. O'Connell ,  Bruce Millar ,  Jean Crepeau ,  Kevin J. Ryan ,  Terry R. Lee ,  Brent Keeth ,  Troy A. Manning ,  Donald N. North ,  Desi Rhoden ,  Henry Stracovsky ,  Yoshikazu Morooka

IPC分类号： G06F1200

CPC分类号： G11C7/1066 ,  G06F13/409 ,  G06F13/4243 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C2207/2254 ,  H05K1/0219 ,  H05K1/0246 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09309 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02D10/14 ,  Y02D10/151

摘要： A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

摘要翻译： SLDRAM系统配备有多个在线可校准存储器模块和用于向存储器模块发出单播和多播命令分组的存储器控​​制器。 命令分组通过单向命令链路发送，该单向命令链路包括一对互补的命令时钟线，命令FLAG线和多个未实现的命令位线。 每个命令时钟线，命令位线和FLAG线都是SLIO传输线。 响应于一个或多个双向数据链路上的命令分组执行数据传送操作，每个双向数据链路包括两对互补的数据时钟线对，以及多个未实现的数据位线。 每个数据时钟线和数据位线都是SLIO传输线。 每个SLIO传输线都是单端端接的，最好采用短截线电阻。