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    Encryption processor with shared memory interconnect
    3.
    发明授权
    Encryption processor with shared memory interconnect 有权
    具有共享内存互连的加密处理器

    公开(公告)号：US06434699B1

    公开(公告)日：2002-08-13

    申请号：US09584930

    申请日：2000-06-01

    申请人： David E. Jones ,  Cormac M. O'Connell

    发明人： David E. Jones ,  Cormac M. O'Connell

    IPC分类号： G06F124

    CPC分类号： G06F7/5324 ,  G06F7/49931 ,  G06F7/5052 ,  G06F7/72 ,  G06F7/722 ,  G06F2207/382 ,  G06F2207/3828 ,  H04L9/14 ,  H04L2209/125

    摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.

    摘要翻译： 加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。 该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。 通过双端口存储器在处理元件之间传送数据。 中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。 通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并以多个周期进行循环。 乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器而在处理元件和中央处理器之间共享。

    Memory devices
    5.
    发明授权
    Memory devices 失效
    内存设备

    公开(公告)号：US5715200A

    公开(公告)日：1998-02-03

    申请号：US682661

    申请日：1996-10-01

    申请人： Dennis A. Fielder ,  James H. Derbyshire ,  Peter B. Gillingham ,  Cormac M. O'Connell ,  Randall R. Torrance

    发明人： Dennis A. Fielder ,  James H. Derbyshire ,  Peter B. Gillingham ,  Cormac M. O'Connell ,  Randall R. Torrance

    IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C7/00 ,  G11C15/00

    CPC分类号： G11C7/1051 ,  G06F12/0893

    摘要： A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.

    摘要翻译： PCT No.PCT / GB95 / 02780 Sec。 371日期：1996年10月1日 102（e）日期1996年10月1日PCT提交1995年11月29日PCT公布。 出版物WO96 / 17354 日期：1996年6月6日具有动态随机存取存储器（DRAM）的存储器件，具有存储元件的多个行和列的阵列; 与DRAM一体形成的高速缓冲存储器，并且包括至少一个具有多个存储元件的寄存器并以与音调匹配的关系连接到DRAM阵列，DRAM的一行中的存储器元件的数量是存储器数量的n倍 所述至少一个寄存器中的元素，n是大于或等于2的整数; 以及用于将至少一个寄存器连接到DRAM的连接器，用于至少一个寄存器的连接器是具有对应于其中的存储器元件的数量的宽度的总线。

    Random access memory with page addressing mode
    6.
    发明授权
    Random access memory with page addressing mode 失效
    具有页寻址模式的随机存取存储器

    公开(公告)号：US5245585A

    公开(公告)日：1993-09-14

    申请号：US604729

    申请日：1990-10-22

    申请人： Peter H. Voss ,  Cormac M. O'Connell

    发明人： Peter H. Voss ,  Cormac M. O'Connell

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C7/1021 ,  G11C7/1033

    摘要： In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.

    Address transition detector circuit
    10.
    发明授权
    Address transition detector circuit 失效
    地址转换检测电路

    公开(公告)号：US5198709A

    公开(公告)日：1993-03-30

    申请号：US721050

    申请日：1991-06-26

    申请人： Cormac M. O'Connell

    发明人： Cormac M. O'Connell

    IPC分类号： G11C11/41 ,  H03K5/1534 ,  H03K19/21

    CPC分类号： H03K5/1534 ,  H03K19/215

    摘要： A semiconductor integrated circuit including a detection circuit (e.g. an address transition detector) for detecting a change of a first and a second input signal. The detection circuit includes a first and a second resettable delay circuit and a gate circuit which is connected thereto. The gate circuit receives directly both the input signals and the output signals of the delay circuits for promptly outputting an output pulse signal with a minimum duration T for all durations of input signals.