公开(公告)号：US08362571B1

公开(公告)日：2013-01-29

申请号：US13016660

申请日：2011-01-28

申请人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

发明人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

IPC分类号： H01L21/02

CPC分类号： H01L21/02115 ,  H01L21/02274 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

摘要： Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.

摘要翻译： 晶体管架构和制造工艺产生通道应变，而不会不利地影响晶体管制造工艺的效率，同时保持材料质量并增强所得晶体管的性能。 产生晶体管应变是使用在至少源极和漏极区上作为覆盖层施加的高度压缩的后自适应硅化物非晶碳覆盖层的PMOS器件。 来自该覆盖层的应力通过源极 - 漏极区域单轴转移到PMOS沟道，以在PMOS沟道中产生压缩应变。

公开(公告)号：US07906817B1

公开(公告)日：2011-03-15

申请号：US12134969

申请日：2008-06-06

申请人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

发明人： Qingguo Wu ,  James S. Sims ,  Mandyam Sriram ,  Seshasayee Varadarajan ,  Haiying Fu ,  Pramod Subramonium ,  Jon Henri ,  Sirish Reddy

IPC分类号： H01L29/76

CPC分类号： H01L21/02115 ,  H01L21/02274 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

摘要： Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.

摘要翻译： 晶体管架构和制造工艺产生通道应变，而不会不利地影响晶体管制造工艺的效率，同时保持材料质量并增强所得晶体管的性能。 产生晶体管应变是使用在至少源极和漏极区上作为覆盖层施加的高度压缩的后自适应硅化物非晶碳覆盖层的PMOS器件。 来自该覆盖层的应力通过源极 - 漏极区域单轴转移到PMOS沟道，以在PMOS沟道中产生压缩应变。

公开(公告)号：US07094713B1

公开(公告)日：2006-08-22

申请号：US10860340

申请日：2004-06-02

申请人： Dong Niu ,  Haiying Fu ,  Brian Lu ,  Feng Wang

发明人： Dong Niu ,  Haiying Fu ,  Brian Lu ,  Feng Wang

IPC分类号： H01L21/26

CPC分类号： C23C16/56 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02348 ,  H01L21/31633 ,  H01L21/31695

摘要： Methods for improving the mechanical properties of a CDO film are provided. The methods involve, for instance, providing either a dense CDO film or a porous CDO film in which the porogen has been removed followed by curing the CDO film at an elevated temperature using either a UV light treatment, an e-beam treatment, or a plasma treatment such that the curing improves the mechanical toughness of the CDO dielectric film.

摘要翻译： 提供了改善CDO膜的机械性能的方法。 所述方法包括例如提供密实的CDO膜或多孔CDO膜，其中致孔剂已被除去，然后使用紫外线光处理，电子束处理或电子束处理在高温下固化CDO膜 等离子体处理使得固化改善了CDO介电膜的机械韧性。

公开(公告)号：USD967444S1

公开(公告)日：2022-10-18

申请号：US29818201

申请日：2021-12-07

申请人： Haiying Fu

设计人： Haiying Fu

公开(公告)号：USD964573S1

公开(公告)日：2022-09-20

申请号：US29829045

申请日：2022-03-02

申请人： Haiying Fu

设计人： Haiying Fu

公开(公告)号：US07968436B1

公开(公告)日：2011-06-28

申请号：US12497322

申请日：2009-07-02

申请人： Yongsik Yu ,  Karen Billington ,  Xingyuan Tang ,  Haiying Fu ,  Michael Carris ,  William Crew

发明人： Yongsik Yu ,  Karen Billington ,  Xingyuan Tang ,  Haiying Fu ,  Michael Carris ,  William Crew

IPC分类号： H01L21/00

CPC分类号： H01L21/76832 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/76834 ,  Y10S257/914 ,  Y10S438/931

摘要： Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

摘要翻译： 具有低介电常数的铜扩散阻挡膜适用于各种铜/金属间电介质集成方案。 根据本发明的铜扩散阻挡膜由一个或多个碳化硅层组成，至少一个碳化硅层具有至少40％碳（C）的组成，例如约45-60％ 碳（C）。 膜的高碳含量层将具有其中C与Si的比率大于2:1的组成; 或> 3：1; 或> 4：1; 或> 5.1。 高碳含量铜扩散阻挡膜相对于常规阻挡材料具有降低的有效k。

公开(公告)号：US07799705B1

公开(公告)日：2010-09-21

申请号：US12348791

申请日：2009-01-05

申请人： Qingguo Wu ,  Haiying Fu ,  David C. Smith ,  David Mordo

发明人： Qingguo Wu ,  Haiying Fu ,  David C. Smith ,  David Mordo

IPC分类号： H01L21/31 ,  H01L21/469 ,  C23C16/40 ,  C23C16/56

CPC分类号： H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348

摘要： Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. In other cases, the structure former precursor has carbon-carbon double or triple bonds and one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. Once the precursor film is formed, the porogen is removed, leaving a porous low-k dielectric matrix with high mechanical strength. Different types of structure former precursors and porogen precursors are described. The resulting low stress low-k porous film may be used as a low-k dielectric film in integrated circuit manufacturing applications.

摘要翻译： 提供了在基片上制备低应力多孔低k介电材料的方法。 所述方法涉及使用具有一个或多个有机官能团的结构前体前体和/或致孔剂前体。 在一些情况下，结构前体具有碳 - 碳双键或三键。 在其他情况下，结构前体前体和致孔剂前体中的一种或两种具有一个或多个大体积的有机基团。 在其他情况下，结构前体具有碳 - 碳双键或三键，结构形成前体和致孔剂前体中的一种或两种具有一个或多个大体积的有机基团。 一旦形成前体膜，去除致孔剂，留下具有高机械强度的多孔低k电介质基质。 描述了不同类型的结构前体前体和致孔剂前体。 所得到的低应力低k多孔膜可用作集成电路制造应用中的低k电介质膜。

公开(公告)号：US07737525B1

公开(公告)日：2010-06-15

申请号：US11936754

申请日：2007-11-07

申请人： Qingguo Wu ,  Haiying Fu ,  Xingyuan Tang

发明人： Qingguo Wu ,  Haiying Fu ,  Xingyuan Tang

IPC分类号： H01L23/00

CPC分类号： C23C16/517 ,  C23C16/401 ,  C23C16/505

摘要： Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules with at least one carbon-carbon triple bond, or carbon-carbon double bond, or a combination of these groups and depositing the carbon doped oxide dielectric layer under conditions in which the resulting dielectric layer has a dielectric constant of not greater than about 2.7.

摘要翻译： 提供了制备具有低介电常数的碳掺杂氧化物（CDO）层的方法。 所述方法包括例如向沉积室提供衬底并将其暴露于具有至少一个碳 - 碳三键或碳 - 碳双键的分子的一个或多个碳掺杂氧化物前体，或其组合 并在所得介电层的介电常数不大于约2.7的条件下沉积碳掺杂的氧化物介电层。

公开(公告)号：US08043667B1

公开(公告)日：2011-10-25

申请号：US12566514

申请日：2009-09-24

申请人： Ananda K. Bandyopadhyay ,  Seon-Mee Cho ,  Haiying Fu ,  Easwar Srinivasan ,  David Mordo

发明人： Ananda K. Bandyopadhyay ,  Seon-Mee Cho ,  Haiying Fu ,  Easwar Srinivasan ,  David Mordo

IPC分类号： B05D3/02 ,  B05D3/06

CPC分类号： H01L21/31633 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31695

摘要： Methods and apparatus for improving mechanical properties of a dielectric film on a substrate are provided. In some embodiments, the dielectric film is a carbon-doped oxide (CDO). The methods involve the use of modulated ultraviolet radiation to increase the mechanical strength while limiting shrinkage and limiting any increases in the dielectric constant of the film. Methods improve film hardness, modulus and cohesive strength, which provide better integration capability and improved performance in the subsequent device fabrication procedures such as chemical mechanical polishing (CMP) and packaging.

摘要翻译： 提供了用于提高基板上的电介质膜的机械特性的方法和装置。 在一些实施例中，电介质膜是碳掺杂氧化物（CDO）。 这些方法涉及使用调制的紫外线辐射来增加机械强度，同时限制收缩并限制膜的介电常数的任何增加。 方法可提高膜的硬度，模量和内聚强度，从而在随后的装置制造程序如化学机械抛光（CMP）和包装中提供更好的整合能力和改进的性能。

公开(公告)号：US07573061B1

公开(公告)日：2009-08-11

申请号：US11893490

申请日：2007-08-15

申请人： Yongsik Yu ,  Karen Billington ,  Xingyuan Tang ,  Haiying Fu ,  Michael Carris ,  William Crew

发明人： Yongsik Yu ,  Karen Billington ,  Xingyuan Tang ,  Haiying Fu ,  Michael Carris ,  William Crew

IPC分类号： H01L35/24 ,  H01L51/00

CPC分类号： H01L21/76832 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/76834 ,  Y10S257/914 ,  Y10S438/931

摘要： Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

摘要翻译： 具有低介电常数的铜扩散阻挡膜适用于各种铜/金属间电介质集成方案。 根据本发明的铜扩散阻挡膜由一个或多个碳化硅层组成，至少一个碳化硅层具有至少40％碳（C）的组成，例如约45-60％ 碳（C）。 膜的高碳含量层将具有其中C与Si的比率大于2:1的组成; 或> 3：1; 或> 4：1; 或> 5.1。 高碳含量铜扩散阻挡膜相对于常规阻挡材料具有降低的有效k。