公开(公告)号：US08307344B2

公开(公告)日：2012-11-06

申请号：US12201037

申请日：2008-08-29

Applicant: Gilbert Laurenti ,  Gary A. Cooper

Inventor： Gilbert Laurenti ,  Gary A. Cooper

IPC: G06F9/44

CPC classification number: G06F11/3636 ,  G06F11/3656

Abstract: In a method for tracing data within an integrated circuit, a default time stamp granularity is selected for a sequence of time stamps, wherein each time stamp has a resolution of 2**N. A sequence of trace events is captured and an elapsed time is determined between each time sequential pair of trace events in the sequence of trace events. A time stamp is formed to associate with each trace event of the sequence of trace events, wherein each time stamp has an associated time stamp granularity, wherein the time stamp has the default time stamp granularity if the elapsed time between a current trace event and a sequentially prior trace event is less than 2**N time slots, otherwise the time stamp granularity is slid to a larger value such that the elapsed time can be represented by N bits, whereby a small number N of bits can accurately represent a large range of elapsed times.

Abstract translation: 在用于跟踪集成电路内的数据的方法中，对于时间戳序列选择默认时间戳粒度，其中每个时间戳具有2 ** N的分辨率。 捕获跟踪事件的序列，并且在跟踪事件序列中的每个时间顺序跟踪事件对之间确定经过的时间。 形成时间戳以与跟踪事件序列的每个跟踪事件相关联，其中每个时间戳具有关联的时间戳粒度，其中如果当前跟踪事件与当前跟踪事件之间的经过时间，则时间戳具有默认时间戳粒度 顺序先前的跟踪事件小于2 ** N个时隙，否则时间戳粒度被滑动到更大的值，使得经过的时间可以由N个比特表示，从而少数N个比特可以精确地表示大范围 经过时间。

公开(公告)号：US08190931B2

公开(公告)日：2012-05-29

申请号：US12478273

申请日：2009-06-04

Applicant: Gilbert Laurenti ,  Dario Cardini

Inventor： Gilbert Laurenti ,  Dario Cardini

IPC: G06F15/00

CPC classification number: G06F11/3648 ,  G06F11/3013 ,  G06F11/3055 ,  G06F11/3093 ,  G06F11/3409 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/86 ,  G06F2201/88 ,  Y02D10/34

Abstract: In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units.

Abstract translation: 在用于监视集成电路内的系统的功率消耗的方法中，在芯片上的系统（SOC）上执行一个或多个软件程序。 在程序执行时，可以响应于执行一个或多个软件程序来调整SOC内的多个功能单元的功率控制设置，由此SOC内的功耗随时间而变化。 功率控制设置可以响应于来自执行软件的显式指示而改变，或者可以响应于SOC内的负载监视控制模块自主地发生。 针对SOC内的多个功能单元报告功率状态序列。 功率状态序列中的每一个可以包括来自多个时钟域的时钟频率，多个电压域的电压电平，启动器活动，目标活动，存储器模块功率使能或多个功能单元中的每一个的功率使能。

公开(公告)号：US20080163017A1

公开(公告)日：2008-07-03

申请号：US11616673

申请日：2006-12-27

Applicant: Lee Larson ,  Gilbert Laurenti

Inventor： Lee Larson ,  Gilbert Laurenti

IPC: G01R31/28

CPC classification number: G06F11/2242

Abstract: A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.

Abstract translation: 一种包括具有控制逻辑的被测系统（SUT）的系统。 SUT还包括耦合到SUT的测试逻辑，并且适于向SUT提供时钟信号以促进测试逻辑和SUT之间的通信。 控制逻辑监视耦合到控制逻辑的扫描链中的多个激活的处理器。 如果激活的处理器的数量减少，则控制逻辑动态地降低时钟信号的频率。

公开(公告)号：US06658578B1

公开(公告)日：2003-12-02

申请号：US09410977

申请日：1999-10-01

Applicant: Gilbert Laurenti ,  Jean-Pierre Giacalone ,  Emmanuel Ego ,  Anne Lombardot ,  Francois Theodorou ,  Gael Clave ,  Yves Masse ,  Karim Djafarian ,  Armelle Laine ,  Jean-Louis Tardieux ,  Eric Ponsot ,  Herve Catan ,  Vincent Gillet ,  Mark Buser ,  Jean-Marc Bachot ,  Eric Badi ,  N. M. Ganesh ,  Walter A. Jackson ,  Jack Rosenzweig ,  Shigeshi Abiko ,  Douglas E. Deao ,  Frederic Nidegger ,  Marc Couvrat ,  Alain Boyadjian ,  Laurent Ichard ,  David Russell

Inventor： Gilbert Laurenti ,  Jean-Pierre Giacalone ,  Emmanuel Ego ,  Anne Lombardot ,  Francois Theodorou ,  Gael Clave ,  Yves Masse ,  Karim Djafarian ,  Armelle Laine ,  Jean-Louis Tardieux ,  Eric Ponsot ,  Herve Catan ,  Vincent Gillet ,  Mark Buser ,  Jean-Marc Bachot ,  Eric Badi ,  N. M. Ganesh ,  Walter A. Jackson ,  Jack Rosenzweig ,  Shigeshi Abiko ,  Douglas E. Deao ,  Frederic Nidegger ,  Marc Couvrat ,  Alain Boyadjian ,  Laurent Ichard ,  David Russell

IPC: G06F132

CPC classification number: G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30083 ,  G06F9/3013 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/325 ,  G06F9/3552 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/3891 ,  G06K13/0825

Abstract: A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Abstract translation: 提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。 架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。 处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。 双乘法累加块提高了处理性能。 存储器接口单元（104）提供对数据和指令存储器的并行访问。 指令缓冲器可用于在执行它之前缓冲单个和复合指令。 解码机构被配置为对来自指令缓冲器的指令进行解码。 使用复合指令可以有效地利用处理器内可用的带宽。 可以从单独的第一和第二编程存储器指令编译软双存储器指令。 可以有条件地执行或重复执行指令。 位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。 处理器包括具有管道保护功能的多级执行管线。 各种功能模块可以单独断电以节省电力。 处理器包括仿真和代码调试功能，支持缓存分析。

公开(公告)号：US06795930B1

公开(公告)日：2004-09-21

申请号：US09716645

申请日：2000-11-20

Applicant: Gilbert Laurenti ,  Olivier Morchipont ,  Laurent Ichard

Inventor： Gilbert Laurenti ,  Olivier Morchipont ,  Laurent Ichard

IPC: G06F126

CPC classification number: G06F9/3853 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/325 ,  G06F9/381 ,  Y02D10/171

Abstract: A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of partitions. A sequence of instructions is executed within an instruction pipeline of the microprocessor. A block of instructions within the sequence of instructions is repetitively executed in response to a local repeat instruction. Either prior to executing the block of instructions, or during the first iteration of the loop, a determination is made that at least one of the plurality of partitions is not needed to execute the block of instructions. Operation of the at least one identified partition is inhibited during the repetitive execution of the block of instructions in order to reduce power dissipation.

Abstract translation: 提供微处理器和操作微处理器的方法，其中微处理器的一部分被分割成多个分区。 在微处理器的指令流水线内执行指令序列。 响应于本地重复指令重复地执行指令序列内的指令块。 在执行指令块之前或在循环的第一次迭代期间，确定执行指令块不需要多个分区中的至少一个分区。 在重复执行指令块期间，禁止至少一个识别的分区的操作，以便降低功耗。

公开(公告)号：US06742110B2

公开(公告)日：2004-05-25

申请号：US09410731

申请日：1999-10-01

Applicant: Karim Djafarian ,  Gilbert Laurenti ,  Vincent Gillet

Inventor： Karim Djafarian ,  Gilbert Laurenti ,  Vincent Gillet

IPC: G06F940

CPC classification number: G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/321 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3859 ,  G06F9/3885 ,  G06F9/3891

Abstract: A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position. Arbitration and merge logic 628, 630 is provided for arbitrating between the first and second control signals and for merging the first and second control signals for controlling power of execution of the instructions in accordance with a set of parallelism rules. A conditional execution unit 634 is responsive to false condition signals from the arbitration and merge logic to inhibit or modify the effect of the control signals. The parallelism rules provide for efficient instruction execution, and the avoidance of resource conflicts.

Abstract translation: 用于并行执行指令的处理引擎10包括用于保持至少两个指令的指令缓冲器600，其中第一指令602处于第一位置，而第二指令604处于第二位置。 第一解码器612提供第一指令的解码并产生第一控制信号。 第一控制信号包括第一资源控制信号，第一地址产生控制信号和指示第一位置的第一指令的有效性的第一有效信号。 第二解码器614提供第二指令的解码并产生第二控制信号。 第二控制信号包括第二资源控制信号，第二地址产生控制信号和指示第二指令在第二位置的有效性的第二有效信号。 提供仲裁和合并逻辑628,630用于在第一和第二控制信号之间进行仲裁，并且用于合并用于根据一组并行规则控制指令的执行功能的第一和第二控制信号。 条件执行单元634响应来自仲裁和合并逻辑的伪状态信号来抑制或修改控制信号的影响。 并行规则提供有效的指令执行和避免资源冲突。

公开(公告)号：US06557097B1

公开(公告)日：2003-04-29

申请号：US09411473

申请日：1999-10-01

Applicant: Gael Clave ,  Karim Djafarian ,  Gilbert Laurenti

Inventor： Gael Clave ,  Karim Djafarian ,  Gilbert Laurenti

IPC: G06F1716

CPC classification number: G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F7/764 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/32 ,  G06F9/321 ,  G06F9/325 ,  G06F9/3552 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/3891 ,  G06F17/16

Abstract: A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation. Each coordinate of an output vector {right arrow over (Y)} can be computed with a N+1 step algorithm, the computation being done with bit test unit operating in parallel with an ALU according to the following equation: ∀ 1 ≤ j ≤ M ⁢   ⁢ Y j = ∑ 1 ≤ i ≤ N ⁢   ⁢ ( ( - 1 ) C i * X ij ) . At a step (i+1)1≦i≦N of the computation, a bit Ci+1 of the CPU register is addressed, this bit is tested in a temporary register and a conditional addition/subtraction of a coordinate of the second input vector Xij is performed.

Abstract translation: 处理引擎10以有效的方式提供输出向量作为具有N个系数的N个输入向量的线性组合的计算。 处理引擎包括用于保持第一输入向量的N个系数中的每一个的表示的系数寄存器940。 提供测试单元950用于测试用于各个系数表示的系数寄存器的选定部分（例如位）。 算术单元970根据系数表示测试的结果，通过选择性地相加/减去第二输入向量的坐标来计算输出向量的各个坐标。 由于与ALU操作并行地使用系数测试操作，所以能够将功耗保持为低。 输出向量的每个坐标{向右箭头（Y可以用N + 1步算法计算，根据以下等式，使用与ALU并行操作的位测试单元进行计算）：在步骤（i + 1 ）1 <= i <= N，CPU寄存器的位Ci + 1被寻址，该位在临时寄存器中被测试，并且执行第二输入向量Xij的坐标的条件相加/减法。

公开(公告)号：US06507921B1

公开(公告)日：2003-01-14

申请号：US09411708

申请日：1999-10-01

Applicant: Mark Buser ,  Gilbert Laurenti ,  Ganesh M. Nandyal

Inventor： Mark Buser ,  Gilbert Laurenti ,  Ganesh M. Nandyal

IPC: G06F1100

CPC classification number: G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30065 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/32 ,  G06F9/321 ,  G06F9/3552 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/3891 ,  G06F11/348 ,  Y02D10/34

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO (800) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M+K, P+Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC13LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P+Q).

Abstract translation: 提供了一种具有可变指令长度的可编程数字信号处理器（DSP）的处理器（100）。 提供跟踪FIFO（800）用于跟踪指令地址序列以辅助软件或硬件调试。 为了节省空间，只有在（M + K，P + Q）之前和刚刚（P，R）之后的指令的地址存储在跟踪FIFO中。 指令长度序列（SEC13LPC）也存储在跟踪FIFO中，使得可以通过在两个不连续点（P到P + Q）之间进行内插来重构指令序列序列。

公开(公告)号：US20120042212A1

公开(公告)日：2012-02-16

申请号：US12859035

申请日：2010-08-18

Applicant: Gilbert Laurenti

Inventor： Gilbert Laurenti

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466 ,  G06F11/364 ,  G06F2201/86

Abstract: A program is executed on a processor to produce execution events. The execution events are traced using a first trace mode during a first portion of the program execution, wherein a portion of trace information for the execution events is omitted from a trace report while tracing in the first trace mode. The mode of tracing is dynamically changed to a second trace mode in response to an event trigger, such that all execution events that occur during the change of mode are captured. Execution events are traced during a second portion of the program execution using the second trace mode, wherein additional trace information for the execution events is included in the trace report while tracing in the second trace mode. The trace mode may be dynamically switched between the two trace modes during execution of the program.

Abstract translation: 在处理器上执行程序以产生执行事件。 在程序执行的第一部分期间，使用第一跟踪模式跟踪执行事件，其中在跟踪报告中从第一跟踪模式中跟踪执行事件的跟踪信息的一部分。 响应于事件触发，跟踪的模式被动态地改变为第二跟踪模式，使得捕获在模式改变期间发生的所有执行事件。 使用第二跟踪模式在程序执行的第二部分期间跟踪执行事件，其中，用于执行事件的附加跟踪信息被包括在跟踪报告中，同时以第二跟踪模式进行跟踪。 跟踪模式可以在程序执行期间在两种跟踪模式之间动态切换。

公开(公告)号：US07509549B2

公开(公告)日：2009-03-24

申请号：US11616673

申请日：2006-12-27

Applicant: Lee Larson ,  Gilbert Laurenti

Inventor： Lee Larson ,  Gilbert Laurenti

IPC: G01R31/28

CPC classification number: G06F11/2242

Abstract: A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.

Abstract translation: 一种包括具有控制逻辑的被测系统（SUT）的系统。 SUT还包括耦合到SUT的测试逻辑，并且适于向SUT提供时钟信号以促进测试逻辑和SUT之间的通信。 控制逻辑监视耦合到控制逻辑的扫描链中的多个激活的处理器。 如果激活的处理器的数量减少，则控制逻辑动态地降低时钟信号的频率。