公开(公告)号：US20110153890A1

公开(公告)日：2011-06-23

申请号：US13037619

申请日：2011-03-01

申请人： Edwin Frank Barry ,  Edward A. Wolff

发明人： Edwin Frank Barry ,  Edward A. Wolff

IPC分类号： G06F13/00

CPC分类号： G06F13/126 ,  G06F13/28

摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

摘要翻译： 描述了用于在数据处理系统内改进数据传输控制的各种有利机制。 描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自治处理器，将DMA指令提取并分派给多个执行单元。 特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。 每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作 单元。 通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。 还描述了可以协作执行“DMA到DMA”传输的传输控制器。 传输控制器可以使用消息级同步来相互同步。

公开(公告)号：US07627698B2

公开(公告)日：2009-12-01

申请号：US11830448

申请日：2007-07-30

申请人： Edwin Franklin Barry ,  Edward A. Wolff

发明人： Edwin Franklin Barry ,  Edward A. Wolff

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/126 ,  G06F13/28

摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

公开(公告)号：US20080235496A1

公开(公告)日：2008-09-25

申请号：US12132001

申请日：2008-06-03

申请人： Gerald George Pechanek ,  Edward A. Wolff

发明人： Gerald George Pechanek ,  Edward A. Wolff

IPC分类号： G06F9/30

CPC分类号： G06F9/30112 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3885

摘要： A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64x64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.

摘要翻译： 描述了包含多个寄存器文件，读和写多路复用器的可扩展可重配置寄存器文件（SRRF）以及响应于指令操作的控制单元。 每个指令支持寄存器文件的多个地址配置，并且在单个指令执行期间可以同时操作不同的配置。 例如，使用大小为32x32的独立文件支持128x32位的配置，每个周期可以运行64x64位和32x128位。 无需增加寄存器文件大小，而不增加寄存器文件读取或写入端口的数量，单个宽度，双宽度，四倍宽度操作数得到最佳支持。

公开(公告)号：US07266620B1

公开(公告)日：2007-09-04

申请号：US10797726

申请日：2004-03-10

申请人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

发明人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.

摘要翻译： 描述具有将数据从外部设备传送到内部存储器的内部存储器的系统核心。 为此，系统核心包括处理器，直接存储器访问（DMA）控制器，指令存储器和多个存储器。 指令存储器包含处理器指令和DMA指令。 DMA控制器从指令存储器中获取DMA指令。 DMA控制器执行所提取的DMA指令，并且由此来自外部设备的数据填充多个存储器。 然后，处理器对在填充的存储器中找到的数据进行操作。

公开(公告)号：US07263624B2

公开(公告)日：2007-08-28

申请号：US11128742

申请日：2005-05-13

申请人： Patrick R. Marchand ,  Gerald George Pechanek ,  Edward A. Wolff

发明人： Patrick R. Marchand ,  Gerald George Pechanek ,  Edward A. Wolff

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3891 ,  Y02D10/128

摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

摘要翻译： 在可扩展数组间接VLIW处理器中提供低功耗架构特性和技术。 这些特征和技术包括可重配置寄存器文件的功率控制，多周期操作的条件功率控制和间接VLIW利用，以及使用ManArray寄存器文件索引机制的基于VLIW的向量处理的功率控制。 这些技术适用于所有处理元件（PE）和阵列控制器序列处理器（SP），以提供显着的功率节省。

公开(公告)号：US07257696B2

公开(公告)日：2007-08-14

申请号：US10641441

申请日：2003-08-15

申请人： Gerald George Pechanek ,  David Strube ,  Edward A. Wolff ,  Edwin Franklin Barry ,  Grayson Morris ,  Carl Donald Busboom ,  Dale Edward Schneider

发明人： Gerald George Pechanek ,  David Strube ,  Edward A. Wolff ,  Edwin Franklin Barry ,  Grayson Morris ,  Carl Donald Busboom ,  Dale Edward Schneider

IPC分类号： G06F9/302

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30149 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3887

摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

摘要翻译： 描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。 在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。 该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作 。 还描述了许多有利的浮点指令。

公开(公告)号：US06965991B1

公开(公告)日：2005-11-15

申请号：US11032799

申请日：2005-01-11

申请人： Patrick R. Marchand ,  Gerald G. Pechanek ,  Edward A. Wolff

发明人： Patrick R. Marchand ,  Gerald G. Pechanek ,  Edward A. Wolff

IPC分类号： G06F1/08 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3891 ,  Y02D10/128

摘要： A reconfigurable register file system is described. The reconfigurable register file system includes an instruction register for storing an instruction specifying an operational requirement, a reconfigurable register file comprising an odd register file having at least one data read port, and an even register file having at least one data read port. The reconfigurable register file system may further suitably include an execution unit connected to the data read ports of the odd and even register files and port usage control logic connected to the instruction register and the reconfigurable register file to control the odd register file and the even register file port address input so that data read port lines change only as needed to support the operational requirement specified by the instruction. The port usage control logic may further include a gating circuit connected to the reconfigurable register files and a clock input, the gating circuit being operable for gating the clock off so no change of state of the reconfigurable register files occurs for each cycle when change is not necessary and gating the clock on so new data is clocked into the reconfigurable register files for each cycle when change is desired.

摘要翻译： 描述可重新配置的寄存器文件系统。 可重构寄存器文件系统包括用于存储指定操作要求的指令的指令寄存器，包括具有至少一个数据读取端口的奇数寄存器文件的可重新配置寄存器文件以及具有至少一个数据读取端口的偶数寄存器文件。 可重配置寄存器文件系统可以进一步适当地包括连接到奇偶寄存器文件的数据读端口的执行单元和连接到指令寄存器和可重配置寄存器堆的端口使用控制逻辑，以控制奇数寄存器堆和偶寄存器 文件端口地址输入，使得数据读取端口线仅在需要时更改以支持指令指定的操作要求。 端口使用控制逻辑还可以包括连接到可重新配置的寄存器文件和时钟输入的选通电路，门控电路可操作以关闭时钟，因此当不是变化时，每个周期不会发生可重新配置的寄存器文件的状态改变 必要和选通时钟，因此，当需要更改时，每个周期将新数据记录到可重新配置的寄存器文件中。

公开(公告)号：US06748517B1

公开(公告)日：2004-06-08

申请号：US09599980

申请日：2000-06-22

申请人： Gerald G. Pechanek ,  David Carl Strube ,  Edwin Frank Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

发明人： Gerald G. Pechanek ,  David Carl Strube ,  Edwin Frank Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

IPC分类号： G06F944

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized testcases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，可以以数据库形式表示指令集的相对容易程度，可以创建工具的准备就绪能力，自检代码的准备生成和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。

公开(公告)号：US06721822B2

公开(公告)日：2004-04-13

申请号：US10254105

申请日：2002-09-24

申请人： Edwin Frank Barry ,  Edward A. Wolff

发明人： Edwin Frank Barry ,  Edward A. Wolff

IPC分类号： G06F1300

CPC分类号： G06F13/126 ,  G06F13/28

摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

摘要翻译： 描述了用于在数据处理系统内改进数据传输控制的各种有利机制。 描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自治处理器，将DMA指令提取并分派给多个执行单元。 特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。 每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作 单元。 通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。 还描述了可以协作执行“DMA到DMA”传输的传输控制器。 传输控制器可以使用消息级同步来相互同步。

公开(公告)号：US06654870B1

公开(公告)日：2003-11-25

申请号：US09598084

申请日：2000-06-21

申请人： Edwin Frank Barry ,  Edward A. Wolff ,  Patrick Rene Marchand ,  David Carl Strube

发明人： Edwin Frank Barry ,  Edward A. Wolff ,  Patrick Rene Marchand ,  David Carl Strube

IPC分类号： G06F938

CPC分类号： G06F9/30141 ,  G06F9/30003 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885

摘要： Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For. example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1. Other unique capabilities result from the present approach to assigning port priorities that improve the performance of the ManArray indirect VLIW processor.

摘要翻译： 端口优先级定义在32位字，16位半字和8位字节的基础上，用于将写使能信号控制到计算寄存器文件（CRF）。 使用歧管阵列（ManArray）可重配置寄存器文件，可以将双字64位和单字32位数据类型指令与其他双字，单字，半字或字节数据混合 类型的指令在相同的很长的指令字（VLIW）内。 通过在VLIW执行期间解决冲突的字节，半字或字的写入优先级冲突，可以使部分操作完成，从而提供有用的功能。 对于。 例如，到32位寄存器R0的半字H0部分的加载半字可以优先完成其操作，而寄存器对R0和R1的64位移位将完成其在非冲突的操作 64位寄存器R0和R1的半字部分。 目前的分配端口优先级方法的其他独特功能来自于提高ManArray间接VLIW处理器的性能。