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    Content-addressable memory module with associative clear
    2.
    发明授权
    Content-addressable memory module with associative clear 失效
    内容可寻址内存模块，具有关联清晰度

    公开(公告)号：US4559618A

    公开(公告)日：1985-12-17

    申请号：US417801

    申请日：1982-09-13

    申请人： David L. Houseman ,  Paul Bowden

    发明人： David L. Houseman ,  Paul Bowden

    IPC分类号： G06F17/30 ,  G11C13/00

    CPC分类号： G06F17/30982

    摘要： A content-addressable memory module which performs an associative clear operation in response to a clear signal provided on a clear line. The associative clear operation simultaneously clears all registers in the content-addressable memory module whose contents match bits in a pattern input to the content-addressable memory module. A mask input along with the pattern determines which bits of the pattern are significant for the match. Each register in the content-addressable memory module has a bidirectional match line associated with it. A register's bidirectional match line carries a match signal only if that register contains data matching the pattern bits specified by the mask and the bidirectional match line is receiving a match signal from an external source. Clearing logic associated with each register clears the register when a clear signal appears on the clear line while the register's bidirectional match line is carrying a match signal. In content-addressable memories constructed of such content-addressable memory modules, memory match lines connect match lines associated with a number of registers. The memory match line and all of the match lines connected to it carry match signals only if each of the registers associated with the match lines contains data matching the pattern and mask input to the content-addressable memory module containing the register. The content-addressable memory module further contains logic allowing the use of encoded addresses to address individual registers in the content-addressable memory module.

    摘要翻译： 一种可内容寻址的存储器模块，其响应于在清晰行上提供的清除信号执行关联清除操作。 关联清除操作同时清除内容可寻址存储器模块中的所有寄存器，其内容与输入到内容寻址存储器模块的模式中的位相匹配。 掩模输入与图案一起确定模式的哪些位对于匹配是重要的。 内容可寻址存储器模块中的每个寄存器具有与其相关联的双向匹配行。 寄存器的双向匹配线仅在该寄存器包含与掩码指定的模式位匹配的数据并且双向匹配线从外部源接收到匹配信号时才携带匹配信号。 清除与每个寄存器相关联的逻辑清除寄存器，当清除信号出现在清除线上时，寄存器的双向匹配线正在携带匹配信号。 在由可内容寻址的存储器模块构成的可内容寻址存储器中，存储器匹配线连接与多个寄存器相关联的匹配线。 只有当与匹配线相关联的每个寄存器都包含匹配包含寄存器的内容可寻址存储器模块的模式和掩码输入的数据时，存储器匹配线和连接到其的所有匹配线才携带匹配信号。 内容可寻址存储器模块还包括允许使用编码地址来寻址内容可寻址存储器模块中的各个寄存器的逻辑。

    Digital data processing system
    4.
    发明授权
    Digital data processing system 失效
    数字数据处理系统

    公开(公告)号：US4493024A

    公开(公告)日：1985-01-08

    申请号：US266406

    申请日：1981-05-22

    申请人： Ward Baxter, II ,  Gerald F. Clancy ,  Ronald H. Gruner ,  Craig J. Mundie ,  Brett L. Bachman ,  Stephen R. Redfield ,  William N. Coder ,  Thomas M. Jones ,  David L. Houseman ,  Charles J. Young ,  Steven M. Haeffele

    发明人： Ward Baxter, II ,  Gerald F. Clancy ,  Ronald H. Gruner ,  Craig J. Mundie ,  Brett L. Bachman ,  Stephen R. Redfield ,  William N. Coder ,  Thomas M. Jones ,  David L. Houseman ,  Charles J. Young ,  Steven M. Haeffele

    IPC分类号： G06F9/318 ,  G06F9/35 ,  G06F13/00

    CPC分类号： G06F9/30192 ,  G06F9/35

    摘要： A data processing system having a flexible internal structure, protected from and effecitvely invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

    摘要翻译： 具有灵活的内部结构的数据处理系统，具有多层次的控制和堆栈机制以及执行多个并发操作的能力，并为用户提供灵活，简化的界面，保护用户不受任何用户无害的影响。 该系统内部由多个独立的独立处理器组成，每个独立的处理器具有单独的微指令控制和至少一个独立于中央通信和存储器节点的独立端口。 通信和存储器节点是具有独立且独立的微指令控制的独立处理器，并且包括能够执行多个并发存储器和通信操作的多个独立操作的微指令控制的处理器。 寻址机制允许永久，唯一的信息识别和所有这些系统可访问和共同的极大的地址空间。 地址与系统物理配置无关。 信息被识别为细粒度级别和信息类型和格式。 保护机制提供与个体信息相关联的可变访问权限。 用户语言指令被转换为方言编码的，统一的中间级指令，以便为所有用户语言提供相同的执行功能。 操作数由统一格式名称引用，通过对用户透明的内部机制转换为地址。

    Digital data processing system respoonsive to instructions containing operation code modifiers
    5.
    发明授权
    Digital data processing system respoonsive to instructions containing operation code modifiers 失效
    数字数据处理系统响应于包含操作代码修改器的指令

    公开(公告)号：US4466057A

    公开(公告)日：1984-08-14

    申请号：US303312

    申请日：1981-09-15

    申请人： David L. Houseman ,  Thomas M. Jones ,  Michael S. Richmond ,  John F. Pilat

    发明人： David L. Houseman ,  Thomas M. Jones ,  Michael S. Richmond ,  John F. Pilat

    IPC分类号： G06F9/318 ,  G06F7/00

    CPC分类号： G06F9/30185 ,  G06F9/3016

    摘要： A system for modifying the manner in which a processor in a digital computer system responds to operation codes in certain instructions. All instructions to which the system responds have operation code syllables containing an operation code and an operation code modifier. In instructions having certain operation codes, the operation code modifier contains a value which modifies the manner in which the processor responds to the operation code. When the processor receives an instruction having such an operation code, a part of the processor which is responsive to the operation code modifier employs the value in the operation code modifier to modify the interpretation of the instruction by the processor. The manner in which the value is employed depends on the operation code. Several uses of the operation code modifier are disclosed. It is used in instructions which have varying numbers of operands to specify the number of operands; it is further used in a branch instruction to calculate the new program value; it is finally used in instructions in which the operation code specifies a set of related operations to specify one operation in the set.

    摘要翻译： 一种用于修改数字计算机系统中的处理器在某些指令中对操作代码进行响应的方式的系统。 系统响应的所有指令都具有包含操作代码和操作代码修饰符的操作代码音节。 在具有某些操作代码的指令中，操作代码修改器包含修改处理器响应于操作代码的方式的值。 当处理器接收到具有这样的操作代码的指令时，响应于操作代码修改器的处理器的一部分使用操作代码修改器中的值来修改处理器对指令的解释。 使用该值的方式取决于操作代码。 公开了操作代码修改器的若干用途。 它用于具有不同数量的操作数的指令中以指定操作数的数量; 在分支指令中进一步用于计算新的程序值; 最终在操作代码指定一组相关操作以指定集合中的一个操作的指令中使用。