公开(公告)号：US20090085167A1

公开(公告)日：2009-04-02

申请号：US12201948

申请日：2008-08-29

Applicant: David Brunco ,  Marc Meuris

Inventor： David Brunco ,  Marc Meuris

IPC: H01L21/321 ,  H01L29/12

CPC classification number: H01L21/28518

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract translation: 本发明涉及半导体处理领域，更具体地说，涉及在锗基片上形成低电阻层。 本发明的一个方面是一种方法，包括：提供其上暴露锗层的至少一个区域的基底; 在衬底和所述锗区域上沉积金属，例如Co或Ni; 在所述金属上形成由氧化硅含有层，氮化硅层或钨层构成的覆盖层，优选为SiO 2层; 然后退火金属锗化物形成; 然后选择性地去除所述覆盖层和任何未反应的金属，其中用于形成所述覆盖层形成的温度低于退火温度。

公开(公告)号：US08354344B2

公开(公告)日：2013-01-15

申请号：US12201948

申请日：2008-08-29

Applicant: David Brunco ,  Marc Meuris

Inventor： David Brunco ,  Marc Meuris

IPC: H01L21/44

CPC classification number: H01L21/28518

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract translation: 本发明涉及半导体处理领域，更具体地说，涉及在锗基片上形成低电阻层。 本发明的一个方面是一种方法，包括：提供其上暴露锗层的至少一个区域的基底; 在衬底和所述锗区域上沉积金属，例如Co或Ni; 在所述金属上形成由氧化硅含有层，氮化硅层或钨层构成的覆盖层，优选为SiO 2层; 然后退火金属锗化物形成; 然后选择性地去除所述覆盖层和任何未反应的金属，其中用于形成所述覆盖层形成的温度低于退火温度。

公开(公告)号：US20080254605A1

公开(公告)日：2008-10-16

申请号：US11735926

申请日：2007-04-16

Applicant: David Brunco ,  Lars-Ake Ragnarsson ,  Stefan De Gendt ,  Zsolt Tokei

Inventor： David Brunco ,  Lars-Ake Ragnarsson ,  Stefan De Gendt ,  Zsolt Tokei

IPC: H01L21/3205

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L29/517

Abstract: One inventive aspect is related to a method of minimizing the final thickness of an interfacial oxide layer between a semiconductor material and a high dielectric constant material. The method comprises depositing a covering layer on the high dielectric constant material. The method further comprises removing adsorbed/absorbed water from the high dielectric constant material prior to depositing the covering layer. The removal of adsorbed/absorbed water is preferably done by a degas treatment. The covering layer may be a gate electrode or a spacer dielectric.

Abstract translation: 一个发明方面涉及使半导体材料和高介电常数材料之间的界面氧化物层的最终厚度最小化的方法。 该方法包括在高介电常数材料上沉积覆盖层。 该方法还包括在沉积覆盖层之前从高介电常数材料中除去吸附/吸收的水。 吸附/吸收的水的去除优选通过脱气处理进行。 覆盖层可以是栅电极或间隔电介质。

公开(公告)号：US20080265380A1

公开(公告)日：2008-10-30

申请号：US12104353

申请日：2008-04-16

Applicant: Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

Inventor： Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

IPC: H01L23/58 ,  H01L21/469

CPC classification number: H01L21/316 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Abstract translation: 本发明的一个方面涉及一种用于制造高k电介质层的方法。 该方法包括在基底上沉积具有第一厚度的高k电介质材料的层。 高k电介质材料具有体积密度值，第一厚度使得高k电介质层具有至少高k电介质材料的体积密度值减去约10％的密度。 该方法还包括将高k电介质层变薄至第二厚度。 另一个发明方面涉及包括通过该方法制造的高k电介质层的半导体器件。

公开(公告)号：US08211812B2

公开(公告)日：2012-07-03

申请号：US12104353

申请日：2008-04-16

Applicant: Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

Inventor： Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/316 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Abstract translation: 本发明的一个方面涉及一种用于制造高k电介质层的方法。 该方法包括在基底上沉积具有第一厚度的高k电介质材料的层。 高k电介质材料具有体积密度值，第一厚度使得高k电介质层具有至少高k电介质材料的体积密度值减去约10％的密度。 该方法还包括将高k电介质层变薄至第二厚度。 另一个发明方面涉及包括通过该方法制造的高k电介质层的半导体器件。

公开(公告)号：US20070032025A1

公开(公告)日：2007-02-08

申请号：US11517654

申请日：2006-09-08

Applicant: David Brunco ,  Karl Opsomer ,  Brice De Jaeger

Inventor： David Brunco ,  Karl Opsomer ,  Brice De Jaeger

IPC: H01L21/336

CPC classification number: H01L21/28518 ,  H01L21/32134 ,  H01L29/41783 ,  H01L29/45

Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.

Abstract translation: 本发明公开了一种在具有暴露的锗和暴露的电介质形貌的基底上形成锗化物的方法，从而允许锗化物形成过程的变化。 该方法包括以下步骤：在具有形貌的基底上沉积镍，执行第一热步骤以将远离地形的区域中的基本上所有沉积的镍转化成锗化物，选择性地除去未反应的镍，并进行第二热步骤以降低 形成的德国的抵抗力。