INTER-PROCESSOR COMMUNICATION TECHNIQUES IN A MULTIPLE-PROCESSOR COMPUTING PLATFORM
    1.
    发明申请
    INTER-PROCESSOR COMMUNICATION TECHNIQUES IN A MULTIPLE-PROCESSOR COMPUTING PLATFORM 有权
    多处理器计算平台中的处理器间通信技术

    公开(公告)号:US20120069035A1

    公开(公告)日:2012-03-22

    申请号:US13235266

    申请日:2011-09-16

    IPC分类号: G06F15/167

    摘要: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

    摘要翻译: 本公开描述了可以在多处理器计算平台内使用的通信技术。 在一些示例中,这些技术可以提供软件接口,其可以用于支持使用命令队列发起任务的多处理器计算平台内的消息传递。 在另外的示例中,这些技术可以提供可用于多处理器计算平台内的共享存储器处理器间通信的软件接口。 在另外的示例中,这些技术可以提供图形处理单元(GPU),其包括用于支持GPU和主机CPU之间的消息传递和/或共享存储器通信的硬件。

    Inter-processor communication techniques in a multiple-processor computing platform
    5.
    发明授权
    Inter-processor communication techniques in a multiple-processor computing platform 有权
    多处理器计算平台中的处理器间通信技术

    公开(公告)号:US08937622B2

    公开(公告)日:2015-01-20

    申请号:US13235266

    申请日:2011-09-16

    摘要: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

    摘要翻译: 本公开描述了可以在多处理器计算平台内使用的通信技术。 在一些示例中,这些技术可以提供软件接口,其可以用于支持使用命令队列发起任务的多处理器计算平台内的消息传递。 在另外的示例中,这些技术可以提供可用于多处理器计算平台内的共享存储器处理器间通信的软件接口。 在另外的示例中,这些技术可以提供图形处理单元(GPU),其包括用于支持GPU和主机CPU之间的消息传递和/或共享存储器通信的硬件。

    Multiple sets of attribute fields within a single page table entry
    7.
    发明授权
    Multiple sets of attribute fields within a single page table entry 有权
    单个页表条目中的多组属性字段

    公开(公告)号:US08938602B2

    公开(公告)日:2015-01-20

    申请号:US13565434

    申请日:2012-08-02

    IPC分类号: G06F12/00 G06F13/00

    摘要: A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.

    摘要翻译: 第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。 公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。 公共页表内的页条目可以包括第一组属性位,其定义第一处理单元对存储块的可访问性;第二组属性位,其定义第二处理单元的相同存储块的可访问性 ,以及定义存储块的物理地址的物理地址位。

    MULTIPLE SETS OF ATTRIBUTE FIELDS WITHIN A SINGLE PAGE TABLE ENTRY
    8.
    发明申请
    MULTIPLE SETS OF ATTRIBUTE FIELDS WITHIN A SINGLE PAGE TABLE ENTRY 有权
    在单页表中多个属性集合

    公开(公告)号:US20140040593A1

    公开(公告)日:2014-02-06

    申请号:US13565434

    申请日:2012-08-02

    IPC分类号: G06F12/10

    摘要: A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.

    摘要翻译: 第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。 公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。 公共页表内的页条目可以包括第一组属性位,其定义第一处理单元对存储块的可访问性;第二组属性位,其定义第二处理单元的相同存储块的可访问性 ,以及定义存储块的物理地址的物理地址位。

    DEFERRED PREEMPTION TECHNIQUES FOR SCHEDULING GRAPHICS PROCESSING UNIT COMMAND STREAMS
    9.
    发明申请
    DEFERRED PREEMPTION TECHNIQUES FOR SCHEDULING GRAPHICS PROCESSING UNIT COMMAND STREAMS 有权
    调度图形处理单元命令流程的延迟预留技术

    公开(公告)号:US20140022266A1

    公开(公告)日:2014-01-23

    申请号:US13554805

    申请日:2012-07-20

    IPC分类号: G06T1/00

    摘要: This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.

    摘要翻译: 本公开涉及用于调度用于在GPU上执行的图形处理单元(GPU)命令流的延迟抢占技术。 描述了被配置为控制GPU执行延迟抢占调度的主机CPU。 例如,主机CPU可以选择GPU命令流中的一个或多个位置作为响应于接收到抢占通知而允许发生抢占的一个或多个位置,并且可以在GPU命令流中放置一个或多个令牌 基于所选择的一个或多个位置。 令牌可以向GPU指示允许在所选择的一个或多个位置发生抢占。 该公开进一步描述了配置成基于放置在GPU命令流中的一个或多个令牌来抢占GPU命令流的执行的GPU。