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1.发明授权公开(公告)号：US08373404B2
公开(公告)日：2013-02-12
申请号：US12591079
申请日：2009-11-06
CPC分类号： H02M3/33507 , H02M3/33523
摘要： A flyback voltage converter includes a transformer having a primary winding and a secondary winding, a switch serially connected to the primary winding for being switched to produce a current in the secondary winding, and a negative lock loop to adjust the peak value of the current in the secondary winding according to a current conduction time during which the current in the secondary winding is higher than a current threshold, such that the peak value of the current in the secondary winding will be in inverse proportion to the time.
摘要翻译： 回扫电压转换器包括具有初级绕组和次级绕组的变压器，串联连接到初级绕组的开关用于切换以产生次级绕组中的电流，以及负锁定环以调整电流的峰值 次级绕组根据次级绕组中的电流的电流导通时间高于电流阈值，使得次级绕组中的电流的峰值将与时间成反比。
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2.发明申请公开(公告)号：US20100117617A1
公开(公告)日：2010-05-13
申请号：US12591079
申请日：2009-11-06
IPC分类号： G05F1/618
CPC分类号： H02M3/33507 , H02M3/33523
摘要： A flyback voltage converter includes a transformer having a primary winding and a secondary winding, a switch serially connected to the primary winding for being switched to produce a current in the secondary winding, and a negative lock loop to adjust the peak value of the current in the secondary winding according to a current conduction time during which the current in the secondary winding is higher than a current threshold, such that the peak value of the current in the secondary winding will be in inverse proportion to the time.
摘要翻译： 回扫电压转换器包括具有初级绕组和次级绕组的变压器，串联连接到初级绕组的开关用于切换以产生次级绕组中的电流，以及负锁定环以调整电流的峰值 次级绕组根据次级绕组中的电流的电流导通时间高于电流阈值，使得次级绕组中的电流的峰值将与时间成反比。
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3.发明授权公开(公告)号：US07619396B2
公开(公告)日：2009-11-17
申请号：US11526624
申请日：2006-09-26
CPC分类号： G05F1/56 , Y10T307/702
摘要： Time-sharing technique is used for power conversion to improve the thermal dissipation thereof. In a power supply arrangement to provide a supply voltage to a load, a plurality of linear regulators are so switched that each time only one of them is enabled to convert an input voltage to the supply voltage, thereby each of them suffering less thermal dissipation.
摘要翻译： 分时技术用于电力转换，以改善其散热。 在向负载提供电源电压的电源装置中，多个线性稳压器被切换，每次只有其中一个能够将输入电压转换成电源电压，从而每个线性稳压器的热耗散较少。
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公开(公告)号：US20090116160A1
公开(公告)日：2009-05-07
申请号：US12318721
申请日：2009-01-07
IPC分类号： H02H3/24
摘要： For protecting a power system, two or three of over current, thermal and under voltage protection circuits are integrated as one protection circuit but operate independently, and one or more protection points thereof are adjusted dynamically in response to detected condition of the power system. Specifically, using voltage and current conditions in the power system to modify the over current protection and the thermal protection maximizes the performance of the power system and covers the process bias in the circuits.
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5.发明申请Load-Dependent Frequency Jittering Circuit and Load-Dependent Frequency Jittering Method 有权负载相关的频率抖动电路和负载相关的频率抖动方法公开(公告)号：US20090115391A1
公开(公告)日：2009-05-07
申请号：US11935558
申请日：2007-11-06
CPC分类号： H03K3/72
摘要： The present invention discloses a load-dependent frequency jittering circuit, comprising: a load condition detection circuit for receiving a switching signal and generating an output according to a load condition; a number generator for receiving the output of the load condition detection circuit and generating a number; a digital to analog converter for converting the output of the number generator to an analog signal; and an oscillator for generating a jittered frequency according to the output of the digital to analog converter.
摘要翻译： 本发明公开了一种负载相关的频率抖动电路，包括：负载状态检测电路，用于接收开关信号并根据负载条件产生输出; 数字发生器，用于接收负载状态检测电路的输出并产生一个数字; 用于将数字发生器的输出转换为模拟信号的数模转换器; 以及用于根据数模转换器的输出产生抖动频率的振荡器。
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公开(公告)号：US20080224782A1
公开(公告)日：2008-09-18
申请号：US11821498
申请日：2007-06-25
IPC分类号： H03L7/099
摘要： A frequency jittering control circuit wherein by means of the characteristics of a PLL whose input switches between different frequencies, the output frequency of the PLL swings between the different frequencies to achieve the desired frequency jittering.
摘要翻译： 一种频率抖动控制电路，其中通过PLL的特性，其输入在不同频率之间切换，PLL的输出频率在不同频率之间摆动，以实现期望的频率抖动。
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7.发明申请公开(公告)号：US20070075690A1
公开(公告)日：2007-04-05
申请号：US11526624
申请日：2006-09-26
IPC分类号： G05F1/00
CPC分类号： G05F1/56 , Y10T307/702
摘要： Time-sharing technique is used for power conversion to improve the thermal dissipation thereof. In a power supply arrangement to provide a supply voltage to a load, a plurality of linear regulators are so switched that each time only one of them is enabled to convert an input voltage to the supply voltage, thereby each of them suffering less thermal dissipation.
摘要翻译： 分时技术用于电力转换，以改善其散热。 在向负载提供电源电压的电源装置中，多个线性稳压器被切换，每次只有其中一个能够将输入电压转换成电源电压，从而每个线性稳压器的热耗散较少。
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公开(公告)号：US20070058310A1
公开(公告)日：2007-03-15
申请号：US11518446
申请日：2006-09-11
IPC分类号： H02H3/20
摘要： For protecting a power system, two or three of over current, thermal and under voltage protection circuits are integrated as one protection circuit but operate independently, and one or more protection points thereof are adjusted dynamically in response to detected condition of the power system. Specifically, using voltage and current conditions in the power system to modify the over current protection and the thermal protection maximizes the performance of the power system and covers the process bias in the circuits.
摘要翻译： 为了保护电力系统，两个或三个过流，过热和欠压保护电路被集成为一个保护电路，但是独立操作，并且响应于电力系统的检测到的状态来动态地调整其一个或多个保护点。 具体来说，使用电力系统中的电压和电流条件修改过电流保护和热保护，最大限度地提高电力系统的性能，并覆盖电路中的过程偏置。
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9.发明授权Constant current source with threshold voltage and channel length modulation compensation 失效具有阈值电压和通道长度调制补偿的恒流源公开(公告)号：US06906651B2
公开(公告)日：2005-06-14
申请号：US10758841
申请日：2004-01-16
申请人： Ching Hsiang Yang , Chun Wei Lin
发明人： Ching Hsiang Yang , Chun Wei Lin
IPC分类号： G05F3/26 , H03K17/041 , H03M1/66
CPC分类号： G05F3/262 , H03K17/04106
摘要： A constant current source with threshold voltage and channel length modulation includes first, second, third, fourth and fifth MOS transistors. Each of the MOS transistors has gate, first and second terminals. The first terminal of the second MOS transistor is coupled to loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and first terminal of the third MOS transistor are together coupled to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage. The gate terminal and second terminal of the fifth MOS transistor are respectively coupled to a second reference voltage and a third reference voltage, and its first terminal is coupled to the gate terminal and first terminal of the third MOS transistor.
摘要翻译： 具有阈值电压和沟道长度调制的恒流源包括第一，第二，第三，第四和第五MOS晶体管。 每个MOS晶体管具有栅极，第一和第二端子。 第二MOS晶体管的第一端子耦合到负载阻抗，并且其第二端子与第一MOS晶体管的第一端子耦合。 第三MOS晶体管的栅极端子和第一端子一起耦合到第二MOS晶体管的栅极端子，并且其第二端子耦合到第四MOS晶体管的第一端子。 第四MOS晶体管的栅极端子和第一端子耦合到第一MOS晶体管的栅极端子，并且其第二端子耦合到第一参考电压。 第五MOS晶体管的栅极端子和第二端子分别耦合到第二参考电压和第三参考电压，并且其第一端子耦合到第三MOS晶体管的栅极端子和第一端子。
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公开(公告)号：US5479128A
公开(公告)日：1995-12-26
申请号：US213852
申请日：1994-03-16
申请人： Yung-Jung Jan , Po-Chuan Huang , Ching-Hsiang Yang
发明人： Yung-Jung Jan , Po-Chuan Huang , Ching-Hsiang Yang
CPC分类号： G11C8/04
摘要： A multiple-delay variable delay circuit uses a random access memory (RAM) array to provide adjustable delay of a block of input data, such as previously necessitated use of an extensive shift register configuration. A single RAM array, having a given capacity, is used to economically provide individual delays to a plurality of blocks of input data, with the aggregate of the individual delays not exceeding the capacity of the single RAM array. Time-shared use of a high speed RAM enables simultaneous single-port processing of data blocks, with delay control circuits providing utilization of separate portions of the RAM capacity, to provide individual delays resulting from successive read/write cycles utilizing a desired total of incremental delays. Simplified delay control circuits provide manufacturing and operating economies with single-port or multi-port RAM arrays.
摘要翻译： 多延迟可变延迟电路使用随机存取存储器（RAM）阵列来提供输入数据块的可调节延迟，诸如先前必须使用的大量移位寄存器配置。 具有给定容量的单个RAM阵列用于经济地向多个输入数据块提供单独的延迟，其中各个延迟的总和不超过单个RAM阵列的容量。 高速RAM的时间共享使用能够同时实现数据块的单端口处理，延迟控制电路提供对RAM容量的分开部分的利用，以提供由连续读/写周期产生的各种延迟，利用所需的总计增量 延误 简化的延迟控制电路为单端口或多端口RAM阵列的制造和运营经济提供了便利。
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