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25 条记录 (耗时 0.021 秒)

    Single ram multiple-delay variable delay circuit
    1.
    发明授权
    Single ram multiple-delay variable delay circuit 失效
    单脉冲多延时可变延迟电路

    公开(公告)号：US5479128A

    公开(公告)日：1995-12-26

    申请号：US213852

    申请日：1994-03-16

    申请人： Yung-Jung Jan ,  Po-Chuan Huang ,  Ching-Hsiang Yang

    发明人： Yung-Jung Jan ,  Po-Chuan Huang ,  Ching-Hsiang Yang

    IPC分类号： G11C8/04 ,  G11C7/00

    CPC分类号： G11C8/04

    摘要： A multiple-delay variable delay circuit uses a random access memory (RAM) array to provide adjustable delay of a block of input data, such as previously necessitated use of an extensive shift register configuration. A single RAM array, having a given capacity, is used to economically provide individual delays to a plurality of blocks of input data, with the aggregate of the individual delays not exceeding the capacity of the single RAM array. Time-shared use of a high speed RAM enables simultaneous single-port processing of data blocks, with delay control circuits providing utilization of separate portions of the RAM capacity, to provide individual delays resulting from successive read/write cycles utilizing a desired total of incremental delays. Simplified delay control circuits provide manufacturing and operating economies with single-port or multi-port RAM arrays.

    摘要翻译： 多延迟可变延迟电路使用随机存取存储器（RAM）阵列来提供输入数据块的可调节延迟，诸如先前必须使用的大量移位寄存器配置。 具有给定容量的单个RAM阵列用于经济地向多个输入数据块提供单独的延迟，其中各个延迟的总和不超过单个RAM阵列的容量。 高速RAM的时间共享使用能够同时实现数据块的单端口处理，延迟控制电路提供对RAM容量的分开部分的利用，以提供由连续读/写周期产生的各种延迟，利用所需的总计增量 延误 简化的延迟控制电路为单端口或多端口RAM阵列的制造和运营经济提供了便利。

    Partial carry-save pipeline multiplier
    2.
    发明授权
    Partial carry-save pipeline multiplier 失效
    部分进位保存管道倍增器

    公开(公告)号：US5457646A

    公开(公告)日：1995-10-10

    申请号：US134068

    申请日：1993-10-12

    申请人： Yi-Feng Jang ,  Ching-Hsiang Yang ,  Po-Chuan Huang

    发明人： Yi-Feng Jang ,  Ching-Hsiang Yang ,  Po-Chuan Huang

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5312 ,  G06F2207/3884

    摘要： A pipeline multiplier is used for multiplying a multiplicand to a multiplier. The pipeline multiplier includes a plurality of adder stages each adder stage includes a partial product processor for processing a partial product of the multiplicand and one of the multiplier. Each of the adder stages further includes a plurality of ripple carry adder (RCA) bands each band includes a plurality of full adders wherein the carry of the full adders ripple sequentially to the most significant full adder in the RCA band. Furthermore, each of the RCA bands in each adder stage includes approximately same number of full adders. The adder stages are further arranged in sequential order such that each of the RCA bands in each stage are pipelined to a corresponding RCA band, which is a RCA band being more-significantly-shifted by one bit, in next adder stage according to the sequential order whereby an accumulative partial product is propagated from one of the adder stages to a next stage. The full adders in each of the RCA band add the partial product from the partial product processing means to the accumulative partial product propagated from last adder stage according to the sequential order. Each of the adder stages further includes a half adder for adding the carry from the RCA band to a bit of the partial product which is the least significant bit of a next more significant RCA band in the adder stage for propagating a processed band-carry to the corresponding RCA band in the next adder stage as the most significant bit of the partial product and to a more significant RCA band in the next adder stage as a carry-in.

    摘要翻译： 使用流水线乘法器将被乘数乘以乘数。 流水线乘法器包括多个加法器级，每个加法器级包括用于处理被乘数和乘数之一的部分乘积的部分乘积处理器。 每个加法器级还包括多个纹波进位加法器（RCA）带，每个波段包括多个完全加法器，其中全加法器的进位顺序波纹到RCA波段中的最高有效全加器。 此外，每个加法器级中的每个RCA频带包括大致相同数量的全加器。 加法器级还按顺序排列，使得每个级中的每个RCA频带被流水线化为相应的RCA频带，RCA频带是在下一个加法阶段根据顺序的一个比特更大幅移位一比特 从而积累的部分积从一个加法器级传播到下一级。 每个RCA频带中的全部加法器将部分乘积处理装置的部分积加到根据顺序的最后一个加法阶段传播的累积部分乘积。 每个加法器级还包括半加法器，用于将来自RCA波段的进位与加法器级中的下一个更高有效RCA波段的最低有效位的部分乘积的比特相加，用于将处理的带载传播到 下一个加法器级中的相应RCA频带作为部分乘积的最高有效位，并作为下一个加法器级的RCA频带作为进位输入。

    Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration
    3.
    发明授权
    Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration 失效
    利用具有多输入和多输出配置的集成存储器件的可变长度延迟电路

    公开(公告)号：US5406518A

    公开(公告)日：1995-04-11

    申请号：US193247

    申请日：1994-02-08

    申请人： Cheng-Yun Sun ,  Yung-Jung Jan ,  Ching-Hsiang Yang

    发明人： Cheng-Yun Sun ,  Yung-Jung Jan ,  Ching-Hsiang Yang

    IPC分类号： G06F5/10 ,  H04N5/073 ,  G11C7/00

    CPC分类号： G06F5/10 ,  H04N5/0736 ,  G06F2205/104

    摘要： The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.

    摘要翻译： 本发明公开了一种用于接收输入数据的有序序列并延迟延迟输出项的输出可变长度延迟时间的装置。 该装置包括用于接收输入数据的有序序列和可变长度延迟时间的输入端口。 该装置还包括集成数据存储器，随机存取存储器（RAM），用于根据与输入数据的有序序列相对应的存储顺序存储输入数据的有序序列。 该装置还包括延迟输出端口，用于根据可变长度延迟时间和存储顺序访问和输出存储装置中的延迟输出项，使得延迟输出项目被延迟可变长度延迟时间 。

    Multi-Voltage headphone drive circuit
    5.
    发明申请
    Multi-Voltage headphone drive circuit 失效
    多电压耳机驱动电路

    公开(公告)号：US20090279713A1

    公开(公告)日：2009-11-12

    申请号：US12460539

    申请日：2009-07-21

    申请人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    发明人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    IPC分类号： H04R1/10

    CPC分类号： H03F3/187 ,  H03F1/0211 ,  H03F3/45475 ,  H03F3/68 ,  H03F2200/516 ,  H04R2460/03

    摘要： The present invention discloses a multi-voltage headphone driver circuit comprising: at least one operational amplifier having an output supplied to a headphone speaker, the operational amplifier receiving a first power supply as its high operation voltage; a charge pump receiving a second power supply to generate a negative voltage corresponding to the second power supply in magnitude; and an m-fold circuit multiplying the negative voltage by m and providing the result to the operational amplifier as a low operation voltage thereof, wherein m is a real number.

    摘要翻译： 本发明公开了一种多电压耳机驱动电路，包括：至少一个运算放大器，具有提供给耳机扬声器的输出，运算放大器接收第一电源作为其高操作电压; 电荷泵接收第二电源以产生与第二电源相对应的负电压; 以及将负电压乘以m并将结果作为其操作电压的运算放大器的m倍电路，其中m是实数。

    Multi-voltage headphone drive circuit
    6.
    发明授权
    Multi-voltage headphone drive circuit 失效
    多电压耳机驱动电路

    公开(公告)号：US08159294B2

    公开(公告)日：2012-04-17

    申请号：US12460539

    申请日：2009-07-21

    申请人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    发明人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    IPC分类号： H03G3/00

    CPC分类号： H03F3/187 ,  H03F1/0211 ,  H03F3/45475 ,  H03F3/68 ,  H03F2200/516 ,  H04R2460/03

    摘要： The present invention discloses a multi-voltage headphone driver circuit comprising: at least one operational amplifier having an output supplied to a headphone speaker, the operational amplifier receiving a first power supply as its high operation voltage; a charge pump receiving a second power supply to generate a negative voltage corresponding to the second power supply in magnitude; and an m-fold circuit multiplying the negative voltage by m and providing the result to the operational amplifier as a low operation voltage thereof, wherein m is a real number.

    摘要翻译： 本发明公开了一种多电压耳机驱动电路，包括：至少一个运算放大器，具有提供给耳机扬声器的输出，运算放大器接收第一电源作为其高操作电压; 电荷泵接收第二电源以产生与第二电源相对应的负电压; 以及将负电压乘以m并将结果作为其操作电压的运算放大器的m倍电路，其中m是实数。

    Arrangement and method for an integrated protection for a power system
    7.
    发明授权
    Arrangement and method for an integrated protection for a power system 有权
    电力系统综合保护的安排和方法

    公开(公告)号：US07907377B2

    公开(公告)日：2011-03-15

    申请号：US12318721

    申请日：2009-01-07

    申请人： Cheng-Hsuan Fan ,  Chao-Hsuan Chuang ,  Hung-Che Chou ,  Ching-Hsiang Yang ,  Chih-Ping Tan

    发明人： Cheng-Hsuan Fan ,  Chao-Hsuan Chuang ,  Hung-Che Chou ,  Ching-Hsiang Yang ,  Chih-Ping Tan

    IPC分类号： H02H3/00 ,  H02H3/24

    CPC分类号： H02H5/041 ,  H02H3/087 ,  H02H3/202

    摘要： For protecting a power system, two or three of over current, thermal and under voltage protection circuits are integrated as one protection circuit but operate independently, and one or more protection points thereof are adjusted dynamically in response to detected condition of the power system. Specifically, using voltage and current conditions in the power system to modify the over current protection and the thermal protection maximizes the performance of the power system and covers the process bias in the circuits.

    摘要翻译： 为了保护电力系统，两个或三个过流，过热和欠压保护电路被集成为一个保护电路，但是独立操作，并且响应于电力系统的检测到的状态来动态地调整其一个或多个保护点。 具体来说，使用电力系统中的电压和电流条件修改过电流保护和热保护，最大限度地提高电力系统的性能，并覆盖电路中的过程偏置。

    Speaker driver circuit driven by positive and negative voltages
    8.
    发明授权
    Speaker driver circuit driven by positive and negative voltages 有权
    扬声器驱动电路由正负电压驱动

    公开(公告)号：US08411879B2

    公开(公告)日：2013-04-02

    申请号：US12507060

    申请日：2009-07-21

    申请人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    发明人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    IPC分类号： H03F99/00 ,  H03F3/04 ,  H04R1/10

    CPC分类号： H03F3/187 ,  H03F1/0211 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H04R2460/03

    摘要： A speaker driver circuit driven by positive and negative voltages, comprising: at least one operational amplifier providing an output to a headphone speaker, and a voltage converter receiving a supplied voltage (VDD), generating r-fold positive and negative voltages (r·VDD and −r·VDD, wherein r is any positive real number except 1) according to the supplied voltage, and supplying the positive and negative voltages to the operational amplifier for its high and low operation voltage levels respectively.

    摘要翻译： 由正负电压驱动的扬声器驱动电路，包括：至少一个运算放大器，为耳机扬声器提供输出;以及电压转换器，接收所提供的电压（VDD），产生r倍的正负电压（r·VDD 和-r·VDD，其中r是除了1）根据所提供的电压之外的任何正实数，并且将正和负电压分别提供给运算放大器用于其高和低操作电压电平。

    Speaker Driver Circuit Driven By Postive and Negative Voltages
    10.
    发明申请
    Speaker Driver Circuit Driven By Postive and Negative Voltages 有权
    扬声器驱动电路由负和负电压驱动

    公开(公告)号：US20090285416A1

    公开(公告)日：2009-11-19

    申请号：US12507060

    申请日：2009-07-21

    申请人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    发明人： Jwin-Yen Guo ,  Ching-Hsiang Yang

    IPC分类号： H03F99/00

    CPC分类号： H03F3/187 ,  H03F1/0211 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H04R2460/03

    摘要： A speaker driver circuit driven by positive and negative voltages, comprising: at least one operational amplifier providing an output to a headphone speaker, and a voltage converter receiving a supplied voltage (VDD), generating r-fold positive and negative voltages (r·VDD and −r·VDD, wherein r is any positive real number except 1) according to the supplied voltage, and supplying the positive and negative voltages to the operational amplifier for its high and low operation voltage levels respectively.

    摘要翻译： 由正和负电压驱动的扬声器驱动电路，包括：向耳机扬声器提供输出的至少一个运算放大器和接收所提供的电压（VDD）的电压转换器，产生r倍的正负电压（r.VDD 和-r.VDD，其中r是除了1）根据所提供的电压之外的任何正实数，并且将正和负电压分别提供给运算放大器用于其高和低操作电压电平。