Method and system for updating firmware of microcontroller
    1.
    发明申请
    Method and system for updating firmware of microcontroller 审中-公开
    更新微控制器固件的方法和系统

    公开(公告)号:US20080307157A1

    公开(公告)日:2008-12-11

    申请号:US11808015

    申请日:2007-06-06

    IPC分类号: G06F12/06 G06F13/38

    CPC分类号: G06F8/65

    摘要: A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I2C or IIC) and a universal serial bus (USB) for the flexibility of using these interfaces. And, a method for updating firmware of a microcontroller is also provided to utilize each interface more efficiently.

    摘要翻译: 用于更新微控制器的固件的系统包括串行外设接口(SPI),内部集成电路(I2C或IIC)和通用串行总线(USB),以便使用这些接口的灵活性。 并且,还提供了一种用于更新微控制器的固件的方法,以更有效地利用每个接口。

    High performance programmable logic system interface and chip
    2.
    发明申请
    High performance programmable logic system interface and chip 审中-公开
    高性能可编程逻辑系统接口和芯片

    公开(公告)号:US20080307135A1

    公开(公告)日:2008-12-11

    申请号:US11808013

    申请日:2007-06-06

    IPC分类号: G06F13/20

    CPC分类号: G06F13/385

    摘要: A chip with a high performance programmable logic system interface, including a first internal device, a second internal device and a bus master, is provided. The first internal device, which is integrated into the chip, communicates with an external device by a first set of internal buses and a first set of external buses. The second internal device, which is integrated into the chip, communicates with the external device by a second set of internal buses and a second set of external buses. The bus master is configured to control the first set of internal buses, the first set of external buses, the second set of internal buses and the second set of external buses. The first internal device and the second internal device communicate with the bus master simultaneously.

    摘要翻译: 提供具有高性能可编程逻辑系统接口的芯片,包括第一内部器件,第二内部器件和总线主器件。 集成在芯片中的第一内部设备通过第一组内部总线和第一组外部总线与外部设备进行通信。 集成到芯片中的第二内部设备通过第二组内部总线和第二组外部总线与外部设备进行通信。 总线主机被配置为控制第一组内部总线,第一组外部总线,第二组内部总线和第二组外部总线。 第一内部设备和第二内部设备同时与总线主站通信。

    Method and system of secured data storage and recovery
    3.
    发明授权
    Method and system of secured data storage and recovery 有权
    安全数据存储和恢复的方法和系统

    公开(公告)号:US08761403B2

    公开(公告)日:2014-06-24

    申请号:US12349524

    申请日:2009-01-07

    IPC分类号: H04L9/08

    摘要: A method and a system of secured data storage and recovery are provided. First, a secured key and an encrypted user password of a storage device are obtained by using a controller of a storage device. Then, the secured key is encrypted by using the encrypted user password to generate a first private key, the encrypted user password is encrypted by using the secured key to generate a second private key, and data to be stored is encrypted by using the secured key. Finally, the encrypted data, the first private key, and the second private key are transmitted to a remote device for storage through a host. Thereby, the security of data storage is enhanced and data recovery mechanism is provided when the storage device is damaged or lost.

    摘要翻译: 提供了一种安全数据存储和恢复的方法和系统。 首先,通过使用存储装置的控制器来获得存储装置的安全密钥和加密的用户密码。 然后,通过使用加密的用户密码对安全密钥进行加密以产生第一私钥,通过使用安全密钥来加密加密的用户密码以生成第二私钥,并且使用安全密钥加密要存储的数据 。 最后,将加密数据,第一私钥和第二私钥发送到远程设备以通过主机进行存储。 从而,增强了数据存储的安全性,并且在存储设备损坏或丢失时提供数据恢复机制。

    METHOD AND SYSTEM OF SECURED DATA STORAGE AND RECOVERY
    4.
    发明申请
    METHOD AND SYSTEM OF SECURED DATA STORAGE AND RECOVERY 有权
    安全数据存储和恢复的方法和系统

    公开(公告)号:US20100100721A1

    公开(公告)日:2010-04-22

    申请号:US12349524

    申请日:2009-01-07

    摘要: A method and a system of secured data storage and recovery are provided. First, a secured key and an encrypted user password of a storage device are obtained by using a controller of a storage device. Then, the secured key is encrypted by using the encrypted user password to generate a first private key, the encrypted user password is encrypted by using the secured key to generate a second private key, and data to be stored is encrypted by using the secured key. Finally, the encrypted data, the first private key, and the second private key are transmitted to a remote device for storage through a host. Thereby, the security of data storage is enhanced and data recovery mechanism is provided when the storage device is damaged or lost.

    摘要翻译: 提供了一种安全数据存储和恢复的方法和系统。 首先,通过使用存储装置的控制器来获得存储装置的安全密钥和加密的用户密码。 然后,通过使用加密的用户密码对安全密钥进行加密以产生第一私钥,通过使用安全密钥来加密加密的用户密码以生成第二私钥,并且使用安全密钥加密要存储的数据 。 最后,将加密数据,第一私钥和第二私钥发送到远程设备以通过主机进行存储。 从而,增强了数据存储的安全性,并且在存储设备损坏或丢失时提供数据恢复机制。

    MEMORY ACCESSING SYSTEM AND METHOD
    5.
    发明申请
    MEMORY ACCESSING SYSTEM AND METHOD 审中-公开
    存储器访问系统和方法

    公开(公告)号:US20080082764A1

    公开(公告)日:2008-04-03

    申请号:US11538253

    申请日:2006-10-03

    IPC分类号: G06F13/00

    CPC分类号: G06F13/4239

    摘要: A memory accessing system, including an internal memory, an external memory, a microprocessor and a controller, is provided. The internal memory is configured to have a program space with a first address range and a data space with a second address range, and the program space and the data space are for source codes and data storage respectively. The external memory is configured to have an external data space with a third address range for storing data, and the third address range covers the first and second address ranges. The microprocessor is configured to process the source codes and data. The controller is configured to control the access of the program space, data space and the external data space.

    摘要翻译: 提供了包括内部存储器,外部存储器,微处理器和控制器的存储器访问系统。 内部存储器被配置为具有具有第一地址范围的程序空间和具有第二地址范围的数据空间,并且程序空间和数据空间分别用于源代码和数据存储。 外部存储器被配置为具有用于存储数据的具有第三地址范围的外部数据空间,并且第三地址范围覆盖第一和第二地址范围。 微处理器配置为处理源代码和数据。 控制器配置为控制程序空间,数据空间和外部数据空间的访问。

    Variable length decoder using serial and parallel processing
    7.
    发明授权
    Variable length decoder using serial and parallel processing 失效
    可变长度解码器采用串并行处理

    公开(公告)号:US5491480A

    公开(公告)日:1996-02-13

    申请号:US249119

    申请日:1994-05-25

    摘要: The present invention is a variable length decoder architecture. A bit-serial variable length decoder (VLD) receives the coded bit stream directly without buffering. The bit serial VLD determines the end of every variable length code word but does not actually decode the code words. The variable length code words are then buffered and decoded by a plurality of VLD's arranged in parallel. High throughout is achieved with a small amount of buffer capacity.

    摘要翻译: 本发明是可变长度解码器架构。 位串行可变长度解码器(VLD)直接接收编码比特流而不进行缓冲。 位串行VLD确定每个可变长度码字的结尾,但实际上并不解码码字。 然后可变长度码字被并行布置的多个VLD缓冲和解码。 通过少量的缓冲容量实现了高可用性。

    Transpose memory for DCT/IDCT circuit
    8.
    发明授权
    Transpose memory for DCT/IDCT circuit 失效
    用于DCT / IDCT电路的转置存储器

    公开(公告)号:US5481487A

    公开(公告)日:1996-01-02

    申请号:US189446

    申请日:1994-01-28

    摘要: A transpose memory is disclosed which has four dual port memories, a first counter for writing elements in the dual port memories and a second counter for reading out elements from the dual port memories. If the received matrix is to be outputted to the first type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element. If the received matrix is to be outputted to the second type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the "evenness" or "oddness" (i.e., divisibleness by two) of the row and column of the matrix element.

    摘要翻译: 公开了一种转置存储器,其具有四个双端口存储器,用于在双端口存储器中写入元件的第一计数器和用于从双端口存储器读出元件的第二计数器。 如果接收的矩阵要输出到第一类型的变换电路,则第一计数器将每个矩阵元素写入分配给矩阵元素的象限的特定双端口存储器中。 如果接收的矩阵要被输出到第二类型的变换电路,则第一个计数器将每个矩阵元素写入分配给该行的“均匀度”或“奇数”(即,二分之二)的特定双端口存储器中, 矩阵元素的列。

    Method for switching Num Lock mode
    9.
    发明授权
    Method for switching Num Lock mode 失效
    Num Lock模式切换方式

    公开(公告)号:US07030783B2

    公开(公告)日:2006-04-18

    申请号:US10459886

    申请日:2003-06-12

    IPC分类号: H03M11/00

    CPC分类号: G06F3/023

    摘要: A method for switching the Num Lock mode of a digital apparatus that is externally coupled with a keypad. When the Num Lock modes of digital apparatus and keypad are different, the keypad transfers the data including a combination code that combines a Num Lock code and a pressed key code to the digital apparatus firstly after any key of the keypad being pressed, and transfers the data including a Num Lock code to the digital apparatus secondly. The main objective of the method according to the present invention is temporally switching Num Lock mode and recovering back to the original mode of the digital apparatus, therefore the input operations of the keypad and the digital apparatus are quite independent and never collision each other.

    摘要翻译: 一种用于切换外部与小键盘耦合的数字设备的数字锁定模式的方法。 当数字设备和键盘的数字锁定模式不同时,键盘将数字包括组合代码,组合数字锁定代码和按下的键码到数字设备,首先按下键盘的任何键,然后传送 其次包括数字设备的数字锁定码的数据。 根据本发明的方法的主要目的是在时间上切换Num Lock模式并恢复到数字设备的原始模式,因此键盘和数字设备的输入操作非常独立,并且不会相互碰撞。

    Integrated portable storage apparatus
    10.
    发明申请
    Integrated portable storage apparatus 审中-公开
    集成便携式存储设备

    公开(公告)号:US20050102471A1

    公开(公告)日:2005-05-12

    申请号:US10891762

    申请日:2004-07-14

    IPC分类号: G06F1/16 G06F3/06 G06F12/00

    摘要: A storage apparatus includes: a body; a serial interface connector, which is mounted to the body to connect with a host externally; and a single chip integrated circuit, which is positioned in the body, integrates a storage media and a serial interface, wherein the serial interface connects to the serial interface connector electrically, and the host is able to access the storage media through the serial interface.

    摘要翻译: 存储装置包括:主体; 串行接口连接器,其安装到主体以外部与主机连接; 并且位于主体中的单芯片集成电路集成存储介质和串行接口,其中串行接口电连接到串行接口连接器,并且主机能够通过串行接口访问存储介质。