公开(公告)号：US5491480A

公开(公告)日：1996-02-13

申请号：US249119

申请日：1994-05-25

Applicant: Yung-Jung Jan ,  Yi-Feng Jang

Inventor： Yung-Jung Jan ,  Yi-Feng Jang

IPC: H03M7/42 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H03M7/40

CPC classification number: H04N19/00 ,  H03M7/425 ,  H04N19/60 ,  H04N19/61 ,  H04N19/13 ,  H04N19/70 ,  H04N19/91

Abstract: The present invention is a variable length decoder architecture. A bit-serial variable length decoder (VLD) receives the coded bit stream directly without buffering. The bit serial VLD determines the end of every variable length code word but does not actually decode the code words. The variable length code words are then buffered and decoded by a plurality of VLD's arranged in parallel. High throughout is achieved with a small amount of buffer capacity.

Abstract translation: 本发明是可变长度解码器架构。 位串行可变长度解码器（VLD）直接接收编码比特流而不进行缓冲。 位串行VLD确定每个可变长度码字的结尾，但实际上并不解码码字。 然后可变长度码字被并行布置的多个VLD缓冲和解码。 通过少量的缓冲容量实现了高可用性。

公开(公告)号：US06980136B2

公开(公告)日：2005-12-27

申请号：US10891764

申请日：2004-07-14

Applicant: Yu-Wei Tsai ,  Yi-Feng Jang

Inventor： Yu-Wei Tsai ,  Yi-Feng Jang

IPC: G06F3/023 ,  H03M11/10 ,  H03M11/00

CPC classification number: H03M11/10 ,  G06F3/023

Abstract: The present invention provides a kind of computer keyboard being able to detect the pressing pressure of keys. The computer keyboard comprises: a plurality of keys; a detecting unit, which outputs a detecting signal according to the pressing pressure of the plurality of keys; and a keyboard controller, which generates a key code according to the detecting signal and sends the key code to a digital device.

Abstract translation: 本发明提供一种能够检测键的按压压力的计算机键盘。 计算机键盘包括：多个键; 检测单元，其根据所述多个键的按压压力输出检测信号; 以及键盘控制器，其根据检测信号生成键码，并将键码发送到数字设备。

公开(公告)号：US20080307157A1

公开(公告)日：2008-12-11

申请号：US11808015

申请日：2007-06-06

Applicant: Yi-Feng Jang ,  Rui-Qing Wei

Inventor： Yi-Feng Jang ,  Rui-Qing Wei

IPC: G06F12/06 ,  G06F13/38

CPC classification number: G06F8/65

Abstract: A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I2C or IIC) and a universal serial bus (USB) for the flexibility of using these interfaces. And, a method for updating firmware of a microcontroller is also provided to utilize each interface more efficiently.

Abstract translation: 用于更新微控制器的固件的系统包括串行外设接口（SPI），内部集成电路（I2C或IIC）和通用串行总线（USB），以便使用这些接口的灵活性。 并且，还提供了一种用于更新微控制器的固件的方法，以更有效地利用每个接口。

公开(公告)号：US20080307135A1

公开(公告)日：2008-12-11

申请号：US11808013

申请日：2007-06-06

Applicant: Yi-Feng Jang ,  Zhi-Jian Liang ,  Hai-Ping Liu ,  Hai-Jun Shu

Inventor： Yi-Feng Jang ,  Zhi-Jian Liang ,  Hai-Ping Liu ,  Hai-Jun Shu

IPC: G06F13/20

CPC classification number: G06F13/385

Abstract: A chip with a high performance programmable logic system interface, including a first internal device, a second internal device and a bus master, is provided. The first internal device, which is integrated into the chip, communicates with an external device by a first set of internal buses and a first set of external buses. The second internal device, which is integrated into the chip, communicates with the external device by a second set of internal buses and a second set of external buses. The bus master is configured to control the first set of internal buses, the first set of external buses, the second set of internal buses and the second set of external buses. The first internal device and the second internal device communicate with the bus master simultaneously.

Abstract translation: 提供具有高性能可编程逻辑系统接口的芯片，包括第一内部器件，第二内部器件和总线主器件。 集成在芯片中的第一内部设备通过第一组内部总线和第一组外部总线与外部设备进行通信。 集成到芯片中的第二内部设备通过第二组内部总线和第二组外部总线与外部设备进行通信。 总线主机被配置为控制第一组内部总线，第一组外部总线，第二组内部总线和第二组外部总线。 第一内部设备和第二内部设备同时与总线主站通信。

公开(公告)号：US07030783B2

公开(公告)日：2006-04-18

申请号：US10459886

申请日：2003-06-12

Applicant: Wei-Yu Kuo ,  Di-Fei Liu ,  Yi-Feng Jang

Inventor： Wei-Yu Kuo ,  Di-Fei Liu ,  Yi-Feng Jang

IPC: H03M11/00

CPC classification number: G06F3/023

Abstract: A method for switching the Num Lock mode of a digital apparatus that is externally coupled with a keypad. When the Num Lock modes of digital apparatus and keypad are different, the keypad transfers the data including a combination code that combines a Num Lock code and a pressed key code to the digital apparatus firstly after any key of the keypad being pressed, and transfers the data including a Num Lock code to the digital apparatus secondly. The main objective of the method according to the present invention is temporally switching Num Lock mode and recovering back to the original mode of the digital apparatus, therefore the input operations of the keypad and the digital apparatus are quite independent and never collision each other.

Abstract translation: 一种用于切换外部与小键盘耦合的数字设备的数字锁定模式的方法。 当数字设备和键盘的数字锁定模式不同时，键盘将数字包括组合代码，组合数字锁定代码和按下的键码到数字设备，首先按下键盘的任何键，然后传送 其次包括数字设备的数字锁定码的数据。 根据本发明的方法的主要目的是在时间上切换Num Lock模式并恢复到数字设备的原始模式，因此键盘和数字设备的输入操作非常独立，并且不会相互碰撞。

公开(公告)号：US20050102471A1

公开(公告)日：2005-05-12

申请号：US10891762

申请日：2004-07-14

Applicant: Yu-Wei Tsai ,  Yi-Feng Jang

Inventor： Yu-Wei Tsai ,  Yi-Feng Jang

IPC: G06F1/16 ,  G06F3/06 ,  G06F12/00

CPC classification number: G06F3/0658 ,  G06F3/0626 ,  G06F3/0679

Abstract: A storage apparatus includes: a body; a serial interface connector, which is mounted to the body to connect with a host externally; and a single chip integrated circuit, which is positioned in the body, integrates a storage media and a serial interface, wherein the serial interface connects to the serial interface connector electrically, and the host is able to access the storage media through the serial interface.

Abstract translation: 存储装置包括：主体; 串行接口连接器，其安装到主体以外部与主机连接; 并且位于主体中的单芯片集成电路集成存储介质和串行接口，其中串行接口电连接到串行接口连接器，并且主机能够通过串行接口访问存储介质。

公开(公告)号：US5663725A

公开(公告)日：1997-09-02

申请号：US555367

申请日：1995-11-08

Applicant: Yi-Feng Jang

Inventor： Yi-Feng Jang

IPC: H03M7/42 ,  H03M7/40

CPC classification number: H03M7/425

Abstract: The present invention relates to a parallel variable length decoder and a method for decoding a signed variable length code word. Variable length decoding (VLD) is a widely-used method in data compression, especially, in the applications of image data communication and storage. Many international standards have adopted this technique in video data compression, for example, JPEG, MPEG, CCITT H.261 and so on. Two programmable logic arrays (PLAs) are used in conventional VLD which differ only in there sign. The present invention uses a single PLA which is triggered by bits of signed fixed length inputs, not including a sign bit. The PLA output an unsigned run-level pair. The VLD processes the sign bit outside the PLA. A mask circuit is used to extract the sign bit which is then combined with the decoded unsigned run-level pair to get a signed run-level pair.

Abstract translation: 本发明涉及一种并行可变长度解码器和一种用于对有符号可变长度码字进行解码的方法。 可变长度解码（VLD）是数据压缩中广泛使用的方法，特别是在图像数据通信和存储应用中。 许多国际标准在视频数据压缩方面采用了这种技术，例如JPEG，MPEG，CCITT H.261等。 在常规VLD中使用两个可编程逻辑阵列（PLA），其中只有符号不同。 本发明使用单个PLA，其由符号固定长度输入的位触发，不包括符号位。 PLA输出未签名的运行级对。 VLD处理PLA外的符号位。 掩码电路用于提取符号位，然后与解码的未签名的运行级对组合以获得签名的运行级对。

公开(公告)号：US5457646A

公开(公告)日：1995-10-10

申请号：US134068

申请日：1993-10-12

Applicant: Yi-Feng Jang ,  Ching-Hsiang Yang ,  Po-Chuan Huang

Inventor： Yi-Feng Jang ,  Ching-Hsiang Yang ,  Po-Chuan Huang

IPC: G06F7/52

CPC classification number: G06F7/5312 ,  G06F2207/3884

Abstract: A pipeline multiplier is used for multiplying a multiplicand to a multiplier. The pipeline multiplier includes a plurality of adder stages each adder stage includes a partial product processor for processing a partial product of the multiplicand and one of the multiplier. Each of the adder stages further includes a plurality of ripple carry adder (RCA) bands each band includes a plurality of full adders wherein the carry of the full adders ripple sequentially to the most significant full adder in the RCA band. Furthermore, each of the RCA bands in each adder stage includes approximately same number of full adders. The adder stages are further arranged in sequential order such that each of the RCA bands in each stage are pipelined to a corresponding RCA band, which is a RCA band being more-significantly-shifted by one bit, in next adder stage according to the sequential order whereby an accumulative partial product is propagated from one of the adder stages to a next stage. The full adders in each of the RCA band add the partial product from the partial product processing means to the accumulative partial product propagated from last adder stage according to the sequential order. Each of the adder stages further includes a half adder for adding the carry from the RCA band to a bit of the partial product which is the least significant bit of a next more significant RCA band in the adder stage for propagating a processed band-carry to the corresponding RCA band in the next adder stage as the most significant bit of the partial product and to a more significant RCA band in the next adder stage as a carry-in.

Abstract translation: 使用流水线乘法器将被乘数乘以乘数。 流水线乘法器包括多个加法器级，每个加法器级包括用于处理被乘数和乘数之一的部分乘积的部分乘积处理器。 每个加法器级还包括多个纹波进位加法器（RCA）带，每个波段包括多个完全加法器，其中全加法器的进位顺序波纹到RCA波段中的最高有效全加器。 此外，每个加法器级中的每个RCA频带包括大致相同数量的全加器。 加法器级还按顺序排列，使得每个级中的每个RCA频带被流水线化为相应的RCA频带，RCA频带是在下一个加法阶段根据顺序的一个比特更大幅移位一比特 从而积累的部分积从一个加法器级传播到下一级。 每个RCA频带中的全部加法器将部分乘积处理装置的部分积加到根据顺序的最后一个加法阶段传播的累积部分乘积。 每个加法器级还包括半加法器，用于将来自RCA波段的进位与加法器级中的下一个更高有效RCA波段的最低有效位的部分乘积的比特相加，用于将处理的带载传播到 下一个加法器级中的相应RCA频带作为部分乘积的最高有效位，并作为下一个加法器级的RCA频带作为进位输入。

公开(公告)号：US08761403B2

公开(公告)日：2014-06-24

申请号：US12349524

申请日：2009-01-07

Applicant: Jin-Chern Su ,  Pao-Hsin Chang ,  Yi-Feng Jang ,  Tien-Chun Tseng

Inventor： Jin-Chern Su ,  Pao-Hsin Chang ,  Yi-Feng Jang ,  Tien-Chun Tseng

IPC: H04L9/08

CPC classification number: H04L9/08 ,  G06F11/1456 ,  G06F11/1469 ,  G06F21/78 ,  H04L9/0891 ,  H04L9/0894

Abstract: A method and a system of secured data storage and recovery are provided. First, a secured key and an encrypted user password of a storage device are obtained by using a controller of a storage device. Then, the secured key is encrypted by using the encrypted user password to generate a first private key, the encrypted user password is encrypted by using the secured key to generate a second private key, and data to be stored is encrypted by using the secured key. Finally, the encrypted data, the first private key, and the second private key are transmitted to a remote device for storage through a host. Thereby, the security of data storage is enhanced and data recovery mechanism is provided when the storage device is damaged or lost.

Abstract translation: 提供了一种安全数据存储和恢复的方法和系统。 首先，通过使用存储装置的控制器来获得存储装置的安全密钥和加密的用户密码。 然后，通过使用加密的用户密码对安全密钥进行加密以产生第一私钥，通过使用安全密钥来加密加密的用户密码以生成第二私钥，并且使用安全密钥加密要存储的数据 。 最后，将加密数据，第一私钥和第二私钥发送到远程设备以通过主机进行存储。 从而，增强了数据存储的安全性，并且在存储设备损坏或丢失时提供数据恢复机制。

公开(公告)号：US20100100721A1

公开(公告)日：2010-04-22

申请号：US12349524

申请日：2009-01-07

Applicant: Jin-Chern Su ,  Pao-Hsin Chang ,  Yi-Feng Jang ,  Tien-Chun Tseng

Inventor： Jin-Chern Su ,  Pao-Hsin Chang ,  Yi-Feng Jang ,  Tien-Chun Tseng

IPC: H04L29/06 ,  H04L9/00 ,  H04L9/08 ,  G06F21/00 ,  H04L9/32 ,  G06F13/00

CPC classification number: H04L9/08 ,  G06F11/1456 ,  G06F11/1469 ,  G06F21/78 ,  H04L9/0891 ,  H04L9/0894

Abstract: A method and a system of secured data storage and recovery are provided. First, a secured key and an encrypted user password of a storage device are obtained by using a controller of a storage device. Then, the secured key is encrypted by using the encrypted user password to generate a first private key, the encrypted user password is encrypted by using the secured key to generate a second private key, and data to be stored is encrypted by using the secured key. Finally, the encrypted data, the first private key, and the second private key are transmitted to a remote device for storage through a host. Thereby, the security of data storage is enhanced and data recovery mechanism is provided when the storage device is damaged or lost.

Abstract translation: 提供了一种安全数据存储和恢复的方法和系统。 首先，通过使用存储装置的控制器来获得存储装置的安全密钥和加密的用户密码。 然后，通过使用加密的用户密码对安全密钥进行加密以产生第一私钥，通过使用安全密钥来加密加密的用户密码以生成第二私钥，并且使用安全密钥加密要存储的数据 。 最后，将加密数据，第一私钥和第二私钥发送到远程设备以通过主机进行存储。 从而，增强了数据存储的安全性，并且在存储设备损坏或丢失时提供数据恢复机制。