公开(公告)号：US08619932B2

公开(公告)日：2013-12-31

申请号：US13109015

申请日：2011-05-17

Applicant: Yu-Wei Lin ,  Chih-Chien Hung ,  Tsang-Yi Wu

Inventor： Yu-Wei Lin ,  Chih-Chien Hung ,  Tsang-Yi Wu

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0091

Abstract: A signal transmission system includes a first clock signal generator and a second clock signal generator. The first clock signal generator is configured for generating a first clock signal according to clock information derived from a transmitted signal, wherein the transmitted signal is changed in response to a frequency change of a second clock signal, and the first clock signal generator enters a frequency-unlocked state if the second clock signal has a frequency transition from a first frequency to a second frequency during a first time period. The second clock signal generator is configured for generating the second clock signal having the frequency transition from the first frequency to the second frequency during a second time period longer than the first time period such that the first clock signal generator stays in a frequency-locked state during the second time period.

Abstract translation: 信号传输系统包括第一时钟信号发生器和第二时钟信号发生器。 第一时钟信号发生器被配置为根据从发送信号导出的时钟信息产生第一时钟信号，其中响应于第二时钟信号的频率变化而发送的信号被改变，并且第一时钟信号发生器输入频率 如果第二时钟信号在第一时间段期间具有从第一频率到第二频率的频率转变，则为非锁定状态。 第二时钟信号发生器被配置为在比第一时间段长的第二时间段内产生具有从第一频率到第二频率的频率转变的第二时钟信号，使得第一时钟信号发生器保持在锁频状态 在第二时期。

公开(公告)号：US07155831B2

公开(公告)日：2007-01-02

申请号：US10889828

申请日：2004-07-12

Applicant: Gwo-Yan Huang ,  Yan-Li Xu ,  Chun He ,  Wu-Kuang Chen ,  Chih-Chien Hung ,  Mu-Chi Hsu ,  Yi-Ta Chung

Inventor： Gwo-Yan Huang ,  Yan-Li Xu ,  Chun He ,  Wu-Kuang Chen ,  Chih-Chien Hung ,  Mu-Chi Hsu ,  Yi-Ta Chung

IPC: B26B9/02

CPC classification number: B26D1/0006 ,  B26D2001/002 ,  B26D2001/0033 ,  B26D2001/0066 ,  Y10T83/929 ,  Y10T83/9319

Abstract: A ceramic cutting tool (100) is for high speed cutting of light, thin and soft materials. The ceramic cutting tool includes an upper blade (10) and a lower blade (20) both made of ceramic material. The upper and lower blades therefore possess extremely high hardness, and excellent wear resistance and heat resistance. This increases an operating lifetime of the ceramic cutting tool. Furthermore, the lower blade can alternatively be a lower blade assembly (30). The lower blade assembly includes a metal base (32), and a ceramic edge insert (31) detachably mounted in the metal base. If the ceramic edge insert becomes worn or is damaged, it can be easily replaced by a new ceramic edge insert. There is no need to replace the metal base.

Abstract translation: 陶瓷切割工具（100）用于高速切割轻薄，柔软的材料。 陶瓷切削工具包括由陶瓷材料制成的上刀片（10）和下刀片（20）。 因此，上下刀片具有非常高的硬度，并且具有优异的耐磨性和耐热性。 这增加了陶瓷切削工具的使用寿命。 此外，下刀片可替代地为下刀片组件（30）。 下刀片组件包括金属基座（32）和可拆卸地安装在金属基座中的陶瓷边缘刀片（31）。 如果陶瓷边缘插入件磨损或损坏，则可以轻松更换新的陶瓷边缘刀片。 没有必要更换金属底座。

公开(公告)号：US06330355B1

公开(公告)日：2001-12-11

申请号：US09283851

申请日：1999-04-01

Applicant: Chia-Hsiang Chen ,  Chih-Chien Hung ,  Han-Ming Sheng ,  Hsiang-Chung Liu ,  Chun-Mei Lee ,  De-Ming Liang ,  Li-Kong Turn ,  Ming-Huei Tseng

Inventor： Chia-Hsiang Chen ,  Chih-Chien Hung ,  Han-Ming Sheng ,  Hsiang-Chung Liu ,  Chun-Mei Lee ,  De-Ming Liang ,  Li-Kong Turn ,  Ming-Huei Tseng

IPC: G06K932

CPC classification number: G03F7/70633

Abstract: A frame layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single chip. One embodiment employs a vernier scale in two orthoginal directions included in the scribeline of both the first chip image and the second chip image. Another embodiment employs a box in box pattern included in the scribeline of both the first chip image and the second chip image. A layer of photoresist on an integrated circuit wafer is exposed with the first and second chip image and the associated monitor images. When the photoresist is developed the overlay accuracy of the first chip image relative to the second chip image can be determined directly from the monitor images in the photoresist.

Abstract translation: 一种帧布局和方法，用于当第一和第二芯片图像用于形成单个芯片时，确定第一芯片图像相对于第二芯片图像的叠加精度。 一个实施例在包括在第一芯片图像和第二芯片图像的划线中的两个正交方向上使用游标刻度。 另一个实施例采用包括在第一芯片图像和第二芯片图像的划线中的盒子模式。 集成电路晶片上的一层光致抗蚀剂用第一和第二芯片图像和相关联的监视器图像曝光。 当光致抗蚀剂显影时，可以直接从光致抗蚀剂中的监视器图像确定第一芯片图像相对于第二芯片图像的覆盖精度。

公开(公告)号：US06261843B1

公开(公告)日：2001-07-17

申请号：US09208933

申请日：1998-12-10

Applicant: Chao-Hsin Chang ,  Hsien-Wen Chang ,  Chih-Chien Hung ,  Kuang-Hui Chang

Inventor： Chao-Hsin Chang ,  Hsien-Wen Chang ,  Chih-Chien Hung ,  Kuang-Hui Chang

IPC: G01N3100

CPC classification number: G01N17/006 ,  G01N2033/0095 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

Abstract translation: 用于监测集成电路晶片的金属腐蚀敏感性的方法和金属测试图案。 形成具有金属圆阵列以模拟接触区域的测试图案，形成用于模拟电极区域的金属条阵列，以及用于模拟体金属区域的覆盖金属层。 使用缺陷扫描系统测量测试图案的每单位面积的第一数量的缺陷。 然后测试图形晶片首次经受环境应力条件，并再次使用缺陷扫描系统测量测试图案的每单位面积的第二数量的缺陷。 将第二个数字和第一个数字之间的差异与临界数字进行比较。 如果发生过度腐蚀，则在继续处理产品晶片之前校正用于生产晶片的工艺。

公开(公告)号：US5998071A

公开(公告)日：1999-12-07

申请号：US48211

申请日：1998-03-26

Applicant: Mingchu King ,  Chih-Chien Hung ,  Shih-Shiung Cheu

Inventor： Mingchu King ,  Chih-Chien Hung ,  Shih-Shiung Cheu

IPC: G03F7/20 ,  G03C5/00

CPC classification number: G03F7/70591 ,  G03F7/70891

Abstract: A low cost, fast method for evaluating the effects of lens heating in a step and repeat projection system is disclosed. The first step is to form a series of photoresist images on a single substrate in the same way as would be done during normal stepping and repeating. The first few images, located centrally, will be produced by a cool lens. As more images are generated, the lens gradually heats up so that the final few images, which are placed alongside the `cool` images, will be produced by a hot lens. Critical dimension bars are present in all image fields (at diagonally opposite corners and in the center), their size in the developed photoresist being an indication of the extent to which the focal plane has drifted. This is then used to compute correction factors for the manufacturer's scaling constants and/or to evaluate the extent, if any, of curvature of field in the projected images.

Abstract translation: 公开了一种用于评估在步骤和重复投影系统中的透镜加热的效果的低成本，快速的方法。 第一步是以与正常步进和重复相同的方式在单个基板上形成一系列光刻胶图像。 位于中央的头几张图像将由一个很酷的镜头制作。 随着产生更多的图像，镜头逐渐加热，以便放置在“酷”图像旁边的最终几个图像将由热镜头产生。 临界尺寸条存在于所有图像领域（在对角线相对的角部和中心），它们在显影的光致抗蚀剂中的尺寸是焦平面漂移程度的指示。 然后将其用于计算制造商缩放常数的校正因子和/或评估投影图像中的曲率的范围（如果有的话）。

公开(公告)号：US5641382A

公开(公告)日：1997-06-24

申请号：US590024

申请日：1996-02-02

Applicant: Tsu Shih ,  Chih-Chien Hung ,  Yuan-Chang Huang

Inventor： Tsu Shih ,  Chih-Chien Hung ,  Yuan-Chang Huang

IPC: H01L21/3213 ,  H01L21/00

CPC classification number: H01L21/32137

Abstract: This invention provides a method for removing metal etch residue of silicon nodules, resulting from a small percentage of silicon in the metal, without causing overetch damage to the photoresist pattern, the metal electrode pattern, or to dielectric layers. The metal conductor layer is partially etched leaving from 20 to 80 percent of the original thickness. Any residue of silicon nodules formed during this partial etching is then removed using ion bombardment. The remainder of the metal conductor layer is then etched. A short overetch period is used to remove any remaining residue of silicon nodules. The overetch period is short and there is no deterioration of the photoresist or exposed edges of the electrode pattern.

Abstract translation: 本发明提供一种从金属中少量的硅产生的硅结节的金属蚀刻残留物的去除，而不会对光致抗蚀剂图案，金属电极图案或介电层造成过蚀刻损伤的方法。 部分蚀刻金属导体层，留下原始厚度的20％至80％。 然后使用离子轰击去除在该部分蚀刻期间形成的任何硅结渣残留物。 然后蚀刻金属导体层的其余部分。 使用短的过氧化物周期来去除任何剩余的硅结节残留物。 过氧化物周期短，并且电极图案的光致抗蚀剂或暴露的边缘没有劣化。

公开(公告)号：US08952718B2

公开(公告)日：2015-02-10

申请号：US13572143

申请日：2012-08-10

Applicant: Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Ping Chen

Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Ping Chen

IPC: H03K19/003 ,  H03K19/00 ,  G11C7/10 ,  G11C11/4093

CPC classification number: H03K19/0005 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/4093

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract translation: 提供了一种由控制器控制的多个存储器的终端电路。 终端电路包括多个驱动器，多个电阻器和多个电容器。 每个驱动器经由传输线耦合到存储器。 每个电阻器经由相应的传输线耦合到相应的驱动器。 每个电容器耦合在相应的电阻器和参考电压之间。 控制器经由驱动器耦合到存储器，并且当经由对应于传输线的传输线传输到存储器的逻辑“0”和逻辑“1”的数量时，控制器向一个驱动器提供特定的代码 其中一个驱动器是不平衡的，以便调整与其中一个驱动器相对应的电容器的终端电压。

公开(公告)号：US20130088929A1

公开(公告)日：2013-04-11

申请号：US13617394

申请日：2012-09-14

Applicant: Yan-Bin LUO ,  Chih-Chien HUNG ,  Qui-Ting CHEN ,  Shang-Ping CHEN

Inventor： Yan-Bin LUO ,  Chih-Chien HUNG ,  Qui-Ting CHEN ,  Shang-Ping CHEN

IPC: G11C7/10

CPC classification number: G06F13/16 ,  G06F1/3275 ,  G06F13/1668 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/06 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

Abstract translation: 提供存储器控制器。 存储器控制器由第一和第二电源供电，并且包括输入/​​输出引脚，驱动器电路，终端电阻器和输入缓冲器。 驱动器电路耦合到输入/输出引脚，并且能够向输入/输出引脚提供写入信号。 端子电阻耦合在输入/输出引脚和第一个电源之间。 输入缓冲器耦合到输入/输出引脚，并能够从输入/输出引脚接收读取信号。 输入/输出引脚和第二个电源之间没有端子电阻耦合。

公开(公告)号：US20090195236A1

公开(公告)日：2009-08-06

申请号：US12026609

申请日：2008-02-06

Applicant: Sy-Chyuan Hwu ,  Chih-Chien Hung

Inventor： Sy-Chyuan Hwu ,  Chih-Chien Hung

IPC: G05F3/08

CPC classification number: G05F3/262

Abstract: Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant.

Abstract translation: 提供了能够减轻由接收的输入信号的变化引起的不期望的影响的半导体电路，其中主电路接收输入信号，并且包括耦合在第一节点和第一电源电压之间的第一电流源，以根据 第一偏置电压。 复制电路耦合到主电路以复制由输入信号的变化引起的第一节点处的电压变化，并且根据重复的变化动态地调整第一偏置电压，使得第一电流保持在常数 。

公开(公告)号：US20050013751A1

公开(公告)日：2005-01-20

申请号：US10894736

申请日：2004-07-19

Applicant: Gwo-Yan Huang ,  Chih-Chien Hung ,  Mu-Chi Hsu ,  Wen Bin Chen ,  Chung-Hsin Lu ,  Wu-Kuang Chen

Inventor： Gwo-Yan Huang ,  Chih-Chien Hung ,  Mu-Chi Hsu ,  Wen Bin Chen ,  Chung-Hsin Lu ,  Wu-Kuang Chen

IPC: B01D53/88 ,  B01J19/12 ,  G06F1/18 ,  B01J19/08

CPC classification number: B01J19/123 ,  B01D53/885 ,  B01D2255/802 ,  G06F1/181

Abstract: An environmentally friendly computer enclosure (20) includes a panel having a vent; and a photocatalyst device (1) mounted on the vent. The photocatalyst device includes an ultraviolet light source device (12), and a filter net (13) with a photocatalyst layer coated thereon. The photocatalyst layer preferably comprises titanium dioxide. The photocatalyst device is mounted on an outside of the vent. The ultraviolet light source device comprises at least one ultraviolet lamp tube or at least one ultraviolet light emitting diode. Soiled air output from the computer enclosure passes through the filter net that is coated with the photocatalyst layer of titanium dioxide. The soiled air is thus purified before being dissipated into the ambient environment.

Abstract translation: 环境友好的计算机外壳（20）包括具有排气口的面板; 和安装在通风口上的光催化剂装置（1）。 光催化剂装置包括紫外光源装置（12）和涂覆有光催化剂层的滤网（13）。 光催化剂层优选包含二氧化钛。 光催化剂装置安装在通风口的外侧。 紫外光源装置包括至少一个紫外线灯管或至少一个紫外线发光二极管。 来自计算机外壳的污染的空气输出通过涂覆有二氧化钛光催化剂层的过滤网。 因此，污染的空气在被消散到周围环境之前被净化。