公开(公告)号：US08948263B2

公开(公告)日：2015-02-03

申请号：US10816118

申请日：2004-04-01

申请人： Ramadas Lakshmikanth Pai ,  Chhavi Kishore ,  Srinivas Cheedella

发明人： Ramadas Lakshmikanth Pai ,  Chhavi Kishore ,  Srinivas Cheedella

IPC分类号： H04N11/02 ,  H04N19/423 ,  H04N19/44 ,  H04N19/61

CPC分类号： H04N19/00484 ,  H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： A video request manager comprises a first state machine. The first state machine commands a memory controller to fetch reference pixels for a first portion of a picture. The second state machine commands a memory controller to write a second portion of the picture.

摘要翻译： 视频请求管理器包括第一状态机。 第一状态机命令存储器控制器来获取图片的第一部分的参考像素。 第二状态机命令存储器控制器写入图像的第二部分。

公开(公告)号：US20060224646A1

公开(公告)日：2006-10-05

申请号：US11095094

申请日：2005-03-30

申请人： Chhavi Kishore ,  Jagannath Shastry

发明人： Chhavi Kishore ,  Jagannath Shastry

IPC分类号： G06F7/00

CPC分类号： H04N19/44 ,  H04N19/70 ,  H04N19/91

摘要： Presented herein are system(s), method(s), and apparatus for converting unsigned fixed length codes to signed fixed length codes. In one embodiment, there is presented a circuit for converting an unsigned code to a signed code. The circuit comprises a multiplexer. The multiplexer comprises a first input, a second input, and an output. The first input receives a first value, the first value being the right shifted unsigned code plus one. The second input receives a second value, the second value being an inverse of a right shifted unsigned code plus one. The output outputs a selected one of the first value received by the first input or the second value received by the second input. The multiplexer selects the selected one of the first value or the second value based on a least significant bit of the unsigned code.

摘要翻译： 本文提出的是将无符号固定长度码转换为签名固定长度码的系统，方法和装置。 在一个实施例中，提供了一种用于将未签名代码转换为签名代码的电路。 该电路包括多路复用器。 多路复用器包括第一输入，第二输入和输出。 第一个输入接收第一个值，第一个值是正确移位的无符号码加1。 第二输入接收第二值，第二值是右移位无符号码加一的倒数。 输出输出由第一输入接收到的第一值中的一个或由第二输入接收的第二值。 多路复用器基于无符号码的最低有效位选择第一值或第二值中的所选择的一个。

公开(公告)号：US07567998B2

公开(公告)日：2009-07-28

申请号：US11172706

申请日：2005-06-29

申请人： Chhavi Kishore ,  Vivek Bhargava ,  Charles Monahan

发明人： Chhavi Kishore ,  Vivek Bhargava ,  Charles Monahan

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/49942

摘要： Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By increasing the number of digits in a multiplication result, partial products within a multiplication can be truncated. When the multiplication result is used in a subsequent operation, the gates required for the increased number of digits in the multiplication result can be made less than the gates saved within the multiply.

摘要翻译： 这里描述了用于乘法器优化的方法和系统。 可以通过该方法和系统来实现不引入附加量化误差的门计数节省。 通过增加乘法结果中的位数，乘法中的部分乘积可以被截断。 当在随后的操作中使用相乘结果时，可以使乘法结果中增加的位数所需的门小于乘法中保存的门数。

公开(公告)号：US07447372B2

公开(公告)日：2008-11-04

申请号：US11092504

申请日：2005-03-29

申请人： Chhavi Kishore ,  Jagannath Sathyanarayana Shastry

发明人： Chhavi Kishore ,  Jagannath Sathyanarayana Shastry

IPC分类号： G06K9/36 ,  H04N7/12 ,  H03M7/40

CPC分类号： H03M7/40

摘要： Presented herein are system(s), method(s), and apparatus for decoding exponential Golomb codes. In one embodiment, there is presented a system for decoding codes having lengths (L) and information bits. The system comprises a circuit and a multiplexer. The circuit provides the information bits of the codes. The multiplexer provides values for the codes, the values for the codes being a function of 2trunc(L/2).

摘要翻译： 这里提出的是用于解码指数哥伦布码的系统，方法和装置。 在一个实施例中，提出了一种用于解码具有长度（L）和信息比特的码的系统。 该系统包括电路和多路复用器。 电路提供代码的信息位。 多路复用器提供代码的值，代码的值是2（SUP / 2）的函数。

公开(公告)号：US07174358B2

公开(公告)日：2007-02-06

申请号：US10414580

申请日：2003-04-15

申请人： Chhavi Kishore ,  Aniruddha Sane

发明人： Chhavi Kishore ,  Aniruddha Sane

IPC分类号： G06F7/52

CPC分类号： G06F5/01 ,  G06F7/535

摘要： A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

摘要翻译： 本发明提供了除数除数和截断除数的系统，方法和装置，其中除数的幅度是2的正幂，例如2×2。 如果除数为正，股息的符号位将被连续x次，并加入股息。 如果除数为负数，则该股利被反转，倒数股息的符号位被连接x次，并加到倒数股利。 除数的符号位也加到和，结果右移x次。 如果除数和股息的符号相同，则在每个右移期间，零被转移到最高有效位。 如果除数和除数的符号不同，则在每个右移期间，加法结果的最高有效位（符号位）被移入最高有效位。

公开(公告)号：US20050036614A1

公开(公告)日：2005-02-17

申请号：US10736125

申请日：2003-12-15

申请人： Ramadas Pai ,  Manoj Vajhallya ,  Chhavi Kishore ,  Bhaskar Sherigar ,  Himakiran Kodihalli ,  Sandeep Bhatia ,  Gaurav Aggarwal ,  Sivagururaman Mahadevan ,  Vijayanand Aralaguppe

发明人： Ramadas Pai ,  Manoj Vajhallya ,  Chhavi Kishore ,  Bhaskar Sherigar ,  Himakiran Kodihalli ,  Sandeep Bhatia ,  Gaurav Aggarwal ,  Sivagururaman Mahadevan ,  Vijayanand Aralaguppe

IPC分类号： G06F13/28 ,  H04N7/167 ,  H04N7/26 ,  H04N7/50

CPC分类号： H04N19/625 ,  H04N19/423 ,  H04N19/503

摘要： Presented herein is a direct memory access engine for providing data words in reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order. A set of multiplexers reverses the bit positions of the words in the local buffer.

摘要翻译： 这里呈现的是用于以相反顺序提供数据字的直接存储器访问引擎。 数据字被分批地取出，包括从最后数据字开始的预定数量的数据字，并进行到第一数据字。 批次存储在本地缓冲区中。 以相反的顺序发送本地缓冲区的内容。 一组多路复用器反转本地缓冲区中的单词的位位置。

公开(公告)号：US07801935B2

公开(公告)日：2010-09-21

申请号：US11095094

申请日：2005-03-30

申请人： Chhavi Kishore ,  Jagannath Sathyanarayana Shastry

发明人： Chhavi Kishore ,  Jagannath Sathyanarayana Shastry

IPC分类号： G06F7/00 ,  G06K9/36

CPC分类号： H04N19/44 ,  H04N19/70 ,  H04N19/91

摘要： Presented herein are system(s), method(s), and apparatus for converting unsigned fixed length codes to signed fixed length codes. In one embodiment, there is presented a circuit for converting an unsigned code to a signed code. The circuit comprises a multiplexer. The multiplexer comprises a first input, a second input, and an output. The first input receives a first value, the first value being the right shifted unsigned code plus one. The second input receives a second value, the second value being an inverse of a right shifted unsigned code plus one. The output outputs a selected one of the first value received by the first input or the second value received by the second input. The multiplexer selects the selected one of the first value or the second value based on a least significant bit of the unsigned code.

摘要翻译： 本文提出的是将无符号固定长度码转换为签名固定长度码的系统，方法和装置。 在一个实施例中，提供了一种用于将未签名代码转换为签名代码的电路。 该电路包括多路复用器。 多路复用器包括第一输入，第二输入和输出。 第一个输入接收第一个值，第一个值是正确移位的无符号码加1。 第二输入接收第二值，第二值是右移位无符号码加一的倒数。 输出输出由第一输入接收到的第一值中的一个或由第二输入接收的第二值。 多路复用器基于无符号码的最低有效位选择第一值或第二值中的所选择的一个。

公开(公告)号：US20060224644A1

公开(公告)日：2006-10-05

申请号：US11092209

申请日：2005-03-29

申请人： Chhavi Kishore ,  Jagannath Shastry

发明人： Chhavi Kishore ,  Jagannath Shastry

IPC分类号： G06F15/00

CPC分类号： H04N19/174 ,  H04N19/61 ,  H04N19/70

摘要： Presented herein are system(s), method(s), and apparatus for detecting end of slice groups in a video bitstream. In one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a bit pointer, a first logic circuit, and a comparator. The multiplexer provides one or more bits from the one or more data words. The bit pointer points to the bits following the provided one or more bits in the one or more data words. The first logic circuit examines at least portions of the data words for an end of data structure code, the at least portions comprising the one or more bits, and provides an indicator indicating the position of the end of data structure code. The comparator compares the indicator to where the bit pointer points.

公开(公告)号：US20060222085A1

公开(公告)日：2006-10-05

申请号：US11095371

申请日：2005-03-30

申请人： Chhavi Kishore

发明人： Chhavi Kishore

IPC分类号： H04B14/04

CPC分类号： H04N19/42 ,  H04N19/174 ,  H04N19/44

摘要： Presented herein are video system(s), method(s), and apparatus for extracting slice groups from data words. According to one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a barrel shifter, another multiplexer, and a bit pointer. The multiplexer divides the one or more data words into a plurality of smaller data words. The barrel shifter shiftings the smaller data words. The other multiplexer provides one or more bits from one or more of the smaller data words. The bit pointer points to a bit following the provided one or more bits in the one or more of the smaller data words.

摘要翻译： 这里呈现的是用于从数据字提取切片组的视频系统，方法和装置。 根据一个实施例，提出了一种用于从一个或多个数据字提取数据结构的电路。 该电路包括多路复用器，桶形移位器，另一多路复用器和位指针。 复用器将一个或多个数据字分成多个较小的数据字。 桶形移位器移动较小的数据字。 另一个复用器从一个或多个较小数据字提供一个或多个位。 位指针指向一个或多个较小数据字中提供的一个或多个位之后的位。

公开(公告)号：US20050232355A1

公开(公告)日：2005-10-20

申请号：US10824897

申请日：2004-04-15

申请人： Srinivas Cheedela ,  Ramadas Pai ,  Chhavi Kishore

发明人： Srinivas Cheedela ,  Ramadas Pai ,  Chhavi Kishore

IPC分类号： H04N7/12 ,  H04N7/26

CPC分类号： H04N19/109 ,  H04N19/15 ,  H04N19/176 ,  H04N19/51

摘要： Presented herein is a video decoder for supporting both single and four motion vector macroblocks. In one embodiment, the video decoder comprises a processor, a motion vector address computer, a video request manager, and a pixel reconstructor. The processor decodes a set of parameters. The set of parameters comprises motion vectors indicating reference pixels associated with the macroblock. The motion vector address computer calculates addresses associated with motion vectors. The video request manager fetches a block of reference pixels at the addresses calculated by the motion vector address computer. The pixel reconstructor reconstructs pixels from the macroblocks. The pixel reconstructor is operable to reconstruct pixels from macroblocks encoded in accordance with a plurality of standards.

摘要翻译： 这里呈现的是用于支持单个和四个运动向量宏块的视频解码器。 在一个实施例中，视频解码器包括处理器，运动矢量地址计算机，视频请求管理器和像素重建器。 处理器解码一组参数。 参数集合包括指示与宏块相关联的参考像素的运动矢量。 运动矢量地址计算机计算与运动矢量相关联的地址。 视频请求管理器在由运动矢量地址计算机计算的地址处获取参考像素块。 像素重建器重建宏块中的像素。 像素重建器可操作以从根据多个标准编码的宏块重构像素。