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公开(公告)号：US08673686B2
公开(公告)日：2014-03-18
申请号：US13492649
申请日：2012-06-08
申请人： Hung-Jen Lee , Shu-Ming Chang , Chen-Han Chiang , Tsang-Yu Liu , Yen-Shih Ho
发明人： Hung-Jen Lee , Shu-Ming Chang , Chen-Han Chiang , Tsang-Yu Liu , Yen-Shih Ho
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , H01L21/561 , H01L21/6836 , H01L23/16 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/13 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/94 , H01L2221/68327 , H01L2221/68377 , H01L2223/5446 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/131 , H01L2224/29011 , H01L2224/29013 , H01L2224/29124 , H01L2224/2957 , H01L2224/296 , H01L2224/3003 , H01L2224/30155 , H01L2224/32225 , H01L2224/73253 , H01L2224/83125 , H01L2224/83127 , H01L2224/83192 , H01L2224/83895 , H01L2224/94 , H01L2924/014 , H01L2924/12041 , H01L2924/1461 , H01L2224/11 , H01L2224/03 , H01L2224/83 , H01L2924/00014 , H01L2924/01032 , H01L2924/00
摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.
摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定多个器件区域的多个预定划线的第一衬底; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环，位于芯片支撑环的周边的切割支撑结构，围绕 所述芯片支撑环分别具有将所述止动环与所述切割支撑结构和所述芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。
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公开(公告)号：US08409925B2
公开(公告)日：2013-04-02
申请号：US13178375
申请日：2011-07-07
申请人： Hung-Jen Lee , Shu-Ming Chang , Chen-Han Chiang , Tsang-Yu Liu , Yen-Shih Ho
发明人： Hung-Jen Lee , Shu-Ming Chang , Chen-Han Chiang , Tsang-Yu Liu , Yen-Shih Ho
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , H01L21/561 , H01L21/6836 , H01L23/16 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/13 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/94 , H01L2221/68327 , H01L2221/68377 , H01L2223/5446 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/131 , H01L2224/29011 , H01L2224/29013 , H01L2224/29124 , H01L2224/2957 , H01L2224/296 , H01L2224/3003 , H01L2224/30155 , H01L2224/32225 , H01L2224/73253 , H01L2224/83125 , H01L2224/83127 , H01L2224/83192 , H01L2224/83895 , H01L2224/94 , H01L2924/014 , H01L2924/12041 , H01L2924/1461 , H01L2224/11 , H01L2224/03 , H01L2224/83 , H01L2924/00014 , H01L2924/01032 , H01L2924/00
摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.
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公开(公告)号：US20120313261A1
公开(公告)日：2012-12-13
申请号：US13492649
申请日：2012-06-08
申请人： Hung-Jen LEE , Shu-Ming CHANG , Chen-Han CHIANG , Tsang-Yu LIU , Yen-Shih HO
发明人： Hung-Jen LEE , Shu-Ming CHANG , Chen-Han CHIANG , Tsang-Yu LIU , Yen-Shih HO
CPC分类号： H01L23/544 , H01L21/561 , H01L21/6836 , H01L23/16 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/13 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/94 , H01L2221/68327 , H01L2221/68377 , H01L2223/5446 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/131 , H01L2224/29011 , H01L2224/29013 , H01L2224/29124 , H01L2224/2957 , H01L2224/296 , H01L2224/3003 , H01L2224/30155 , H01L2224/32225 , H01L2224/73253 , H01L2224/83125 , H01L2224/83127 , H01L2224/83192 , H01L2224/83895 , H01L2224/94 , H01L2924/014 , H01L2924/12041 , H01L2924/1461 , H01L2224/11 , H01L2224/03 , H01L2224/83 , H01L2924/00014 , H01L2924/01032 , H01L2924/00
摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.
摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定多个器件区域的多个预定划线的第一衬底; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环，位于芯片支撑环的周边的切割支撑结构，围绕 所述芯片支撑环分别具有将所述止动环与所述切割支撑结构和所述芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。
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公开(公告)号：US08836134B2
公开(公告)日：2014-09-16
申请号：US13738082
申请日：2013-01-10
申请人： Po-Shen Lin , Chuan-Jin Shiu , Bing-Siang Chen , Chen-Han Chiang , Chien-Hui Chen , Hsi-Chien Lin , Yen-Shih Ho
发明人： Po-Shen Lin , Chuan-Jin Shiu , Bing-Siang Chen , Chen-Han Chiang , Chien-Hui Chen , Hsi-Chien Lin , Yen-Shih Ho
CPC分类号： H01L21/78 , B81C1/00888 , H01L21/561 , H01L23/12 , H01L23/3114 , H01L23/562 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/1461 , H01L2924/16235 , H01L2924/00
摘要： A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.
摘要翻译： 提供一种制造半导体堆叠封装的方法。 在晶片和基板上进行单晶化处理，晶片和晶片被堆叠在其上。 去除切割区域上的晶片的一部分，以在晶片的芯片的边缘上形成应力集中区域。 然后切割晶片和基板，并且迫使应力集中在晶片的芯片的边缘上。 结果，芯片的边缘变形。 因此，防止了应力延伸到芯片的内部。 还提供半导体堆叠封装。
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公开(公告)号：US20120313222A1
公开(公告)日：2012-12-13
申请号：US13178375
申请日：2011-07-07
申请人： Hung-Jen LEE , Shu-Ming CHANG , Chen-Han CHIANG , Tsang-Yu LIU , Yen-Shih HO
发明人： Hung-Jen LEE , Shu-Ming CHANG , Chen-Han CHIANG , Tsang-Yu LIU , Yen-Shih HO
CPC分类号： H01L23/544 , H01L21/561 , H01L21/6836 , H01L23/16 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/13 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/94 , H01L2221/68327 , H01L2221/68377 , H01L2223/5446 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/131 , H01L2224/29011 , H01L2224/29013 , H01L2224/29124 , H01L2224/2957 , H01L2224/296 , H01L2224/3003 , H01L2224/30155 , H01L2224/32225 , H01L2224/73253 , H01L2224/83125 , H01L2224/83127 , H01L2224/83192 , H01L2224/83895 , H01L2224/94 , H01L2924/014 , H01L2924/12041 , H01L2924/1461 , H01L2224/11 , H01L2224/03 , H01L2224/83 , H01L2924/00014 , H01L2924/01032 , H01L2924/00
摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.
摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。
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